Re: [PATCH v7 0/2] arm64: dts: intel: agilex5: enable USB3.1 on SoCDK

[Dinh Nguyen]

On 9/11/26 04:09, adrian.ho.yin.ng@xxxxxxxxxx wrote:
> From: Adrian Ng Ho Yin <adrian.ho.yin.ng@xxxxxxxxxx>
>
> Add the Agilex5 USB3.1 DWC3 controller node and enable it in host mode on
> the SoCDK board. Place the controller under a simple-bus with a 40-bit
> dma-ranges window so the DMA/IOMMU stack respects the interconnect address
> width when SMMU is enabled.
>
> The SoCDK daughter card only exposes the USB3.1 interface, so the unused
> USB0 (DWC2) board enablement is removed in a follow-up patch.
>
> This DTS series is posted separately from the USB bindings/driver series
> ("[PATCH v7 0/2] usb: dwc3: add Altera Agilex5 DWC3 support"). Depends on
> compatible "altr,agilex5-dwc3" from that series:
> https://lore.kernel.org/all/cover.1789114385.git.adrian.ho.yin.ng@xxxxxxxxxx/
>
> ---
> changelog:
> v6->v7:
> * Split out of the USB series into a standalone DTS posting.
>
> USB v7 series:
> https://lore.kernel.org/all/cover.1789114385.git.adrian.ho.yin.ng@xxxxxxxxxx/
>
> Previous combined series (v6):
> https://lore.kernel.org/all/cover.1788886615.git.adrian.ho.yin.ng@xxxxxxxxxx/
> ---
>
> Adrian Ng Ho Yin (2):
>    arm64: dts: intel: agilex5: add USB3.1 controller node
>    arm64: dts: intel: agilex5: remove usb0 in Agilex5 SoCDK
Applied!

Thanks,
Dinh