Re: [PATCH RFC v3 04/12] net: pcs: add NXP SerDes XPCS shared core

[Maxime Chevallier]

Hi Jan,

On 9/19/26 08:54, Jan Petrous via B4 Relay wrote:
> From: Clark Wang <xiaoning.wang@xxxxxxx>
> 
> The SerDes subsystems found on NXP S32G and i.MX SoCs integrate a
> Synopsys DesignWare Ethernet XPCS and an Ethernet PHY (PMA) with an
> identical register layout. Only the register transport differs: indirect
> memory mapped access on S32G, Clause 45 MDIO on i.MX.
> 
> Add a transport agnostic phylink PCS core which operates on regmaps
> provided by the platform glue. It implements the phylink PCS operations,
> the Clause 37 SGMII / 2500BASE-X / USXGMII / 10GBASE-R configuration and
> link state handling, soft reset and polling helpers, and the common
> feature sets. The platform specific register sequences, compatibility
> tables and quirks are supplied through a per revision descriptor by the
> platform drivers selecting this core.
> 
> The register sequences and the feature lists are derived from the
> Synopsys pcs-xpcs driver, so its copyright is retained. A separate driver
> is needed because struct dw_xpcs is built around an mdio_device and owns
> the transport, the reset and the identification of a standalone PCS,
> while here the PMA can be shared with a PCIe controller, the bring-up is
> sequenced across both XPCS instances by the SerDes PHY driver, and the
> transport is not always MDIO.

Is there a way to avoid code duplication by wrapping the accesses into
a mii_bus ?

This is what the Rockchip submission does : 

https://lore.kernel.org/r/20260919125119.2107089-8-coiaprant@xxxxxxxxx

Maxime