[PATCH 09/11] arm64: dts: qcom: ipq5424: Wire up PPE clock to GCC
From: Kathiravan Thirumoorthy
Date: Mon Sep 21 2026 - 02:21:44 EST
Add the PPE 375 MHz clock generated by the CMN PLL to the GCC clock
controller inputs. GCC uses this clock as the source for the NSS
MEMNOC clocks.
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/ipq5424.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index 95e2508ac145..64a06d615d61 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -486,7 +486,8 @@ gcc: clock-controller@1800000 {
<&pcie1_phy>,
<&pcie2_phy>,
<&pcie3_phy>,
- <&ssphy_0>;
+ <&ssphy_0>,
+ <&cmn_pll IPQ5424_PPE_375MHZ_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#interconnect-cells = <1>;
--
2.34.1