[PATCH] arm64: dts: qcom: nord: Add LLCC node
From: Shawn Guo
Date: Tue Sep 22 2026 - 05:56:24 EST
From: Anurag Pateriya <anurag.pateriya@xxxxxxxxxxxxxxxx>
Add the system cache controller. All sixteen banks are listed, four per
DDR slice at 0x100000 strides from slice + 0x800000, followed by the
global broadcast OR/AND regions, which the driver expects at the reg
indices right after the last bank.
No ECC interrupt is described, as the Nord interrupt map does not expose
one for the LLCC. The driver treats it as optional.
Signed-off-by: Anurag Pateriya <anurag.pateriya@xxxxxxxxxxxxxxxx>
Signed-off-by: Shawn Guo <shengchao.guo@xxxxxxxxxxxxxxxx>
---
Dependencies:
- LLCC driver: https://lore.kernel.org/all/20260910-nord_llcc-v1-0-30fd1cca65fe@xxxxxxxxxxxxxxxx/
arch/arm64/boot/dts/qcom/nord.dtsi | 40 ++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
index e0496fd40c30..6896bda14ef3 100644
--- a/arch/arm64/boot/dts/qcom/nord.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord.dtsi
@@ -2071,6 +2071,46 @@ watchdog@17826000 {
clocks = <&sleep_clk>;
interrupts = <GIC_ESPI 848 IRQ_TYPE_EDGE_RISING>;
};
+
+ llcc: system-cache-controller@21800000 {
+ compatible = "qcom,nord-llcc";
+ reg = <0x0 0x21800000 0x0 0x100000>,
+ <0x0 0x21a00000 0x0 0x100000>,
+ <0x0 0x21c00000 0x0 0x100000>,
+ <0x0 0x21e00000 0x0 0x100000>,
+ <0x0 0x22800000 0x0 0x100000>,
+ <0x0 0x22a00000 0x0 0x100000>,
+ <0x0 0x22c00000 0x0 0x100000>,
+ <0x0 0x22e00000 0x0 0x100000>,
+ <0x0 0x23800000 0x0 0x100000>,
+ <0x0 0x23a00000 0x0 0x100000>,
+ <0x0 0x23c00000 0x0 0x100000>,
+ <0x0 0x23e00000 0x0 0x100000>,
+ <0x0 0x24800000 0x0 0x100000>,
+ <0x0 0x24a00000 0x0 0x100000>,
+ <0x0 0x24c00000 0x0 0x100000>,
+ <0x0 0x24e00000 0x0 0x100000>,
+ <0x0 0x20400000 0x0 0x100000>,
+ <0x0 0x20600000 0x0 0x100000>;
+ reg-names = "llcc0_base",
+ "llcc1_base",
+ "llcc2_base",
+ "llcc3_base",
+ "llcc4_base",
+ "llcc5_base",
+ "llcc6_base",
+ "llcc7_base",
+ "llcc8_base",
+ "llcc9_base",
+ "llcc10_base",
+ "llcc11_base",
+ "llcc12_base",
+ "llcc13_base",
+ "llcc14_base",
+ "llcc15_base",
+ "llcc_broadcast_base",
+ "llcc_broadcast_and_base";
+ };
};
arch_timer: timer {
--
2.43.0