[PATCH v3] arm64: dts: ti: k3-pinctrl: Add virtual GPIO select mux macros
From: Akashdeep Kaur
Date: Tue Sep 22 2026 - 06:33:19 EST
Add virtual GPIO select mux macros for configuring the vgpio_sel
field in pad configuration registers. This field selects GPIO
controller routing. The meaning of each value is SoC-specific -
refer to the Technical Reference Manual for the specific SoC.
For example, on AM62L, values 0 and 1 select GPIO controller 0 and 2
respectively, while on J784S4, values 0-3 select different GPIO
controller pairs based on the pin. Pad configuration register
field details can be found in each SoC's Technical Reference
Manual (example: section 14.2.1.2.1 of [1]).
[1] AM62L TRM: https://www.ti.com/lit/ug/sprujb4a/sprujb4a.pdf
Signed-off-by: Akashdeep Kaur <a-kaur@xxxxxx>
---
K3 SoC vgpio_sel Field Audit:
All supported SoCs use bits [5:4] for vgpio_sel field.
Supported SoCs:
- J721E, J721S2, J7200, J784S4: 4 options (0-3) for MAIN GPIO,
2 options (0-1) for WKUP GPIO
- AM62L: 2 options (0-1)
Not supported (field reserved):
- AM62X, AM62AX, AM62PX, AM62D, AM64X, AM65X, J722S
Changes in v3:
- Use tabs for macro alignment
- Add comment warning that field is SoC specific
- Link to v2: https://lore.kernel.org/all/20260921063505.3986565-1-a-kaur@xxxxxx/
Changes in v2:
- Add all four PIN_VGPIO_SEL[0-3] macros instead of just two
- Use generic value-based naming to support all K3 SoCs
- Update commit message to clarify SoC-specific behavior
- Link to v1: https://lore.kernel.org/all/20260917111539.3844577-1-a-kaur@xxxxxx/
---
arch/arm64/boot/dts/ti/k3-pinctrl.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h
index 4491898d8294..e8ca69a97b65 100644
--- a/arch/arm64/boot/dts/ti/k3-pinctrl.h
+++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h
@@ -8,6 +8,7 @@
#ifndef DTS_ARM64_TI_K3_PINCTRL_H
#define DTS_ARM64_TI_K3_PINCTRL_H
+#define VGPIO_SEL_SHIFT (4)
#define WKUP_LVL_EN_SHIFT (7)
#define WKUP_LVL_POL_SHIFT (8)
#define DEBOUNCE_SHIFT (11)
@@ -111,6 +112,15 @@
#define PIN_WKUP_EN_LEVEL_HIGH (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_HIGH)
#define PIN_WKUP_EN (WKUP_ENABLE | WKUP_ON_EDGE)
+/*
+ * SoC-specific field - Refer to the SoC Technical Reference Manual to
+ * determine which GPIO controller each value selects.
+ */
+#define PIN_VGPIO_SEL0 (0 << VGPIO_SEL_SHIFT)
+#define PIN_VGPIO_SEL1 (1 << VGPIO_SEL_SHIFT)
+#define PIN_VGPIO_SEL2 (2 << VGPIO_SEL_SHIFT)
+#define PIN_VGPIO_SEL3 (3 << VGPIO_SEL_SHIFT)
+
/* Default mux configuration for gpio-ranges to use with pinctrl */
#define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7)
--
2.34.1