[PATCH v1] arm64: dts: qcom: glymur-crd: Enable DMIC4 and DMIC5 on CRD
From: Mohammad Rafi Shaik
Date: Tue Sep 22 2026 - 07:05:00 EST
Add the LPASS LPI pinctrl state for the third DMIC clock line, which
drives DMIC4 and DMIC5.
CRD has additional digital microphones connected to this clock line, so
reference the new pinctrl state from the VA macro and route the
microphone bias supply to DMIC4 and DMIC5 to make them usable.
Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 6 ++++--
arch/arm64/boot/dts/qcom/glymur.dtsi | 16 ++++++++++++++++
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
index ccdc322157e0..02e342ecfe4a 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
@@ -247,7 +247,9 @@ sound {
"VA DMIC0", "vdd-micb",
"VA DMIC1", "vdd-micb",
"VA DMIC2", "vdd-micb",
- "VA DMIC3", "vdd-micb";
+ "VA DMIC3", "vdd-micb",
+ "VA DMIC4", "vdd-micb",
+ "VA DMIC5", "vdd-micb";
wsa-dai-link {
link-name = "WSA Playback";
@@ -695,7 +697,7 @@ touchscreen@38 {
};
&lpass_vamacro {
- pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+ pinctrl-0 = <&dmic01_default>, <&dmic23_default>, <&dmic45_default>;
pinctrl-names = "default";
qcom,dmic-sample-rate = <4800000>;
vdd-micb-supply = <&vreg_l1b_e0_1p8>;
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index de7c395d9c35..c941b473ce25 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -4768,6 +4768,22 @@ data-pins {
};
};
+ dmic45_default: dmic45-default-state {
+ clk-pins {
+ pins = "gpio17";
+ function = "dmic4_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ data-pins {
+ pins = "gpio18";
+ function = "dmic4_data";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
wsa_swr_active: wsa-swr-active-state {
clk-pins {
pins = "gpio10";
--
2.34.1