[PATCH 1/4] mmc: sdhci-cadence6: add PHY settle delay after tuning DLL re-lock

[tze . yee . ng]

From: Tze Yee Ng <tze.yee.ng@xxxxxxxxxx>

After re-locking the DLL, allow the same 5 to 5.5 ms for the clock and
PHY signals to stabilize as sdhci_cdns6_phy_init() does. Without this
settle time the command issued immediately after tuning (e.g. the R1b
CMD6 that switches eMMC from HS200 down to HS during HS400 selection)
can time out.

Signed-off-by: Tze Yee Ng <tze.yee.ng@xxxxxxxxxx>
---
 drivers/mmc/host/sdhci-cadence-phy-v6.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mmc/host/sdhci-cadence-phy-v6.c b/drivers/mmc/host/sdhci-cadence-phy-v6.c
index 22d56bb46d75..35f35ef9c710 100644
--- a/drivers/mmc/host/sdhci-cadence-phy-v6.c
+++ b/drivers/mmc/host/sdhci-cadence-phy-v6.c
@@ -811,6 +811,9 @@ int sdhci_cdns6_set_tune_val(struct sdhci_host *host, unsigned int val)
 	if (ret)
 		dev_warn(mmc_dev(host->mmc), "%s: DLL reset release failed: %d\n", __func__, ret);
 
+	/* Allow 5 to 5.5 ms for clock and PHY signals to stabilize after configuration */
+	usleep_range(5000, 5500);
+
 	return ret;
 }
 
-- 
2.43.7