RE: [PATCH v24 08/15] mmc: renesas_sdhi: Add TMIO_MMC_INTERNAL_DIVIDER flag

[Biju Das]

Hi Wolfram,

> -----Original Message-----
> From: Biju Das
> Sent: 07 September 2026 08:20
> Subject: RE: [PATCH v24 08/15] mmc: renesas_sdhi: Add TMIO_MMC_INTERNAL_DIVIDER flag
> 
> Hi Wolfram,
> 
> Thanks for the feedback.
> 
> > -----Original Message-----
> > From: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
> > Sent: 03 September 2026 10:44
> > Subject: Re: [PATCH v24 08/15] mmc: renesas_sdhi: Add
> > TMIO_MMC_INTERNAL_DIVIDER flag
> >
> >
> > > +static bool renesas_sdhi_is_internal_divider_enabled(struct
> > > +tmio_mmc_host *host) {
> > > +	bool enable = false;
> > > +
> > > +	if (host->pdata->flags & TMIO_MMC_INTERNAL_DIVIDER)
> > > +		enable = true;
> > > +
> > > +	return enable;
> > > +}
> > > +
> > > +static unsigned int renesas_sdhi_clk_get_rate(struct tmio_mmc_host *host,
> > > +					      struct clk *clk)
> > > +{
> > > +	unsigned int freq = clk_get_rate(clk);
> > > +
> > > +	if (renesas_sdhi_is_internal_divider_enabled(host))
> > > +		freq /= 2;
> > > +
> > > +	return freq;
> > > +}
> >
> > ???
> >
> > static unsigned int renesas_sdhi_clk_get_rate(struct tmio_mmc_host *host,
> > 					      struct clk *clk)
> > {
> > 	unsigned int freq = clk_get_rate(clk);
> >
> > 	return host->pdata->flags & TMIO_MMC_INTERNAL_DIVIDER ? freq / 2 :
> > freq; }
> >
> > Was this AI generated?
> 
> I kept 2 function as renesas_sdhi_is_internal_divider_enabled() is reused in
> renesas_sdhi_set_clock()while adding support for HS400 mode.
> 
> Currently, we decided to focus only for basic RZ/G3L support. So I can merge it into Single function as
> you suggested.
> 
> >
> > > @@ -184,10 +205,14 @@ static unsigned int
> > > renesas_sdhi_clk_update(struct tmio_mmc_host *host,
> > >
> > >  	clk_set_rate(ref_clk, best_freq);
> > >
> > > -	if (priv->clkh)
> > > +	if (priv->clkh) {
> > > +		if (host->pdata->flags & TMIO_MMC_INTERNAL_DIVIDER)
> > > +			clkh_shift = 1;
> >
> > No, this needs to be handled a bit above where clkh_shift is initially
> > set up, so we have it all in one block.
> 
> There is a difference here.
> 
> SDx_Clock (HS clk) Figure 4.4-8 Block Diagram of the Deformed Clock System (7) IMCLK = SDx_Clock/2
> 
> SD_Clock  Figure 6.2-2 Functional Diagram of Clock Divider for SD_CLK
> 
> Currently framework request a clk to set, we set HS clk first, followed by SD_CLK.
> 
> On RZ/G3L, SD_CLK value is based on internal divider.
> 
> For HS400 mode, SD_CLK = SDx_Clock(HS clk)/2
> 
> For Non-HS400 mode, SD_CLK = SDx_Clock(HS clk)/4
> 
> I don't find an easy way to move this logic to the above.
> 
> Please share your thoughts on this.

Gentle ping.

Cheers,
Biju