[PATCH v3 2/4] gpu: nova-core: falcon: Extract PRISCV register
From: Antonin Malzieu Ridolfi via B4 Relay
Date: Tue Sep 22 2026 - 21:14:52 EST
From: Antonin Malzieu Ridolfi <dev@xxxxxxxxxxx>
Move PRISCV register definitions from the root regs.rs file into the
falcon module that own them, in the existing falcon/regs.rs file.
This follows the same pattern established by previous commits for
GSP, PDISP, PFB, PBUS, PMC and PFSP registers: register definitions
move to the module that interprets their service, visibility changes
to pub(super).
Since PFALCON, PFALCON2 and FUSE registers are defined in the root
regs.rs but are also part of the falcon interface, accessed by the
whole falcon module, they are re-exported in falcon/regs.rs so falcon
code can use a single regs:: prefix.
Once these families moves out of the root module, these re-exports
will become plain definitions.
Suggested-by: Alexandre Courbot <acourbot@xxxxxxxxxx>
Suggested-by: Danilo Krummrich <dakr@xxxxxxxxxx>
Signed-off-by: Antonin Malzieu Ridolfi <dev@xxxxxxxxxxx>
---
drivers/gpu/nova-core/falcon/hal/ga102.rs | 2 +-
drivers/gpu/nova-core/falcon/hal/tu102.rs | 12 +++----
drivers/gpu/nova-core/falcon/regs.rs | 58 +++++++++++++++++++++++++------
drivers/gpu/nova-core/regs.rs | 29 +---------------
4 files changed, 54 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova-core/falcon/hal/ga102.rs
index f9a8444cf840..7323579a478d 100644
--- a/drivers/gpu/nova-core/falcon/hal/ga102.rs
+++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs
@@ -18,6 +18,7 @@
driver::Bar0,
falcon::{
hal::LoadMethod,
+ regs, //
Falcon,
FalconBromParams,
FalconEngine,
@@ -25,7 +26,6 @@
PFalcon2Registers,
PeregrineCoreSelect, //
},
- regs,
};
use super::FalconHal;
diff --git a/drivers/gpu/nova-core/falcon/hal/tu102.rs b/drivers/gpu/nova-core/falcon/hal/tu102.rs
index 7fc6e83c2566..068258c69fd9 100644
--- a/drivers/gpu/nova-core/falcon/hal/tu102.rs
+++ b/drivers/gpu/nova-core/falcon/hal/tu102.rs
@@ -11,14 +11,12 @@
time::Delta, //
};
-use crate::{
- falcon::{
- hal::LoadMethod,
- Falcon,
- FalconBromParams,
- FalconEngine, //
- },
+use crate::falcon::{
+ hal::LoadMethod,
regs, //
+ Falcon,
+ FalconBromParams,
+ FalconEngine,
};
use super::FalconHal;
diff --git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/falcon/regs.rs
index 336f065929db..ac4a02405927 100644
--- a/drivers/gpu/nova-core/falcon/regs.rs
+++ b/drivers/gpu/nova-core/falcon/regs.rs
@@ -3,6 +3,37 @@
use crate::driver::NovaRegisters;
use kernel::io::register;
+use crate::falcon::{
+ PFalcon2Registers,
+ PeregrineCoreSelect, //
+};
+
+// PRISCV
+
+register! {
+ base: PFalcon2Registers;
+
+ /// RISC-V status register for debug (Turing and GA100 only).
+ /// Reflects current RISC-V core status.
+ pub(super) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ 0x00000240 {
+ /// RISC-V core active/inactive status.
+ 0:0 active_stat => bool;
+ }
+
+ /// GA102 and later.
+ pub(super) NV_PRISCV_RISCV_CPUCTL(u32) @ 0x00000388 {
+ 7:7 active_stat => bool;
+ 4:4 halted => bool;
+ }
+
+ /// GA102 and later.
+ pub(super) NV_PRISCV_RISCV_BCR_CTRL(u32) @ 0x00000668 {
+ 8:8 br_fetch => bool;
+ 4:4 core_select => PeregrineCoreSelect;
+ 0:0 valid => bool;
+ }
+}
+
// FSP (Foundation Security Processor) queue registers for Hopper/Blackwell Chain of Trust.
// These registers manage falcon EMEM communication queues.
@@ -26,17 +57,22 @@
}
}
-// PFALCON registers are defined in the root `regs.rs` but are part of the falcon
-// interface, accessed by the whole falcon module. They are re-exported here so
-// falcon code can use a single `regs::` prefix.
-// Once the PFALCON family moves out of the root module, these re-exports become
+// PFALCON, PFALCON2 and FUSE registers are defined in the root `regs.rs` but
+// are part of the falcon interface, accessed by the whole falcon module. They
+// are re-exported here so falcon code can use a single `regs::` prefix.
+// Once these families move out of the root module, these re-exports become
// plain definitions.
pub(super) use crate::regs::{
- NV_PFALCON_FALCON_BOOTVEC, NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON_CPUCTL_ALIAS,
- NV_PFALCON_FALCON_DMACTL, NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FALCON_DMATRFBASE1,
- NV_PFALCON_FALCON_DMATRFCMD, NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCON_FALCON_DMATRFMOFFS,
- NV_PFALCON_FALCON_DMEMC, NV_PFALCON_FALCON_DMEMD, NV_PFALCON_FALCON_EMEMC,
- NV_PFALCON_FALCON_EMEMD, NV_PFALCON_FALCON_IMEMC, NV_PFALCON_FALCON_IMEMD,
- NV_PFALCON_FALCON_IMEMT, NV_PFALCON_FALCON_MAILBOX0, NV_PFALCON_FALCON_MAILBOX1,
- NV_PFALCON_FALCON_OS, NV_PFALCON_FALCON_RM, NV_PFALCON_FBIF_CTL, NV_PFALCON_FBIF_TRANSCFG,
+ NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION, NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION,
+ NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION, NV_FUSE_OPT_FPF_SIZE,
+ NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID, NV_PFALCON2_FALCON_BROM_ENGIDMASK,
+ NV_PFALCON2_FALCON_BROM_PARAADDR, NV_PFALCON2_FALCON_MOD_SEL, NV_PFALCON_FALCON_BOOTVEC,
+ NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON_CPUCTL_ALIAS, NV_PFALCON_FALCON_DMACTL,
+ NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FALCON_DMATRFBASE1, NV_PFALCON_FALCON_DMATRFCMD,
+ NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCON_FALCON_DMATRFMOFFS, NV_PFALCON_FALCON_DMEMC,
+ NV_PFALCON_FALCON_DMEMD, NV_PFALCON_FALCON_EMEMC, NV_PFALCON_FALCON_EMEMD,
+ NV_PFALCON_FALCON_ENGINE, NV_PFALCON_FALCON_HWCFG2, NV_PFALCON_FALCON_IMEMC,
+ NV_PFALCON_FALCON_IMEMD, NV_PFALCON_FALCON_IMEMT, NV_PFALCON_FALCON_MAILBOX0,
+ NV_PFALCON_FALCON_MAILBOX1, NV_PFALCON_FALCON_OS, NV_PFALCON_FALCON_RM, NV_PFALCON_FBIF_CTL,
+ NV_PFALCON_FBIF_TRANSCFG,
};
diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index 693b5148b1d8..0a168b53236d 100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -24,8 +24,7 @@
FalconModSelAlgo,
FalconSecurityModel,
PFalcon2Registers,
- PFalconRegisters,
- PeregrineCoreSelect, //
+ PFalconRegisters, //
},
mm::tlb::TlbAckMode, //
};
@@ -346,32 +345,6 @@ pub(crate) fn mem_scrubbing_done(self) -> bool {
}
}
-// PRISCV
-
-register! {
- base: PFalcon2Registers;
-
- /// RISC-V status register for debug (Turing and GA100 only).
- /// Reflects current RISC-V core status.
- pub(crate) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ 0x00000240 {
- /// RISC-V core active/inactive status.
- 0:0 active_stat => bool;
- }
-
- /// GA102 and later.
- pub(crate) NV_PRISCV_RISCV_CPUCTL(u32) @ 0x00000388 {
- 7:7 active_stat => bool;
- 4:4 halted => bool;
- }
-
- /// GA102 and later.
- pub(crate) NV_PRISCV_RISCV_BCR_CTRL(u32) @ 0x00000668 {
- 8:8 br_fetch => bool;
- 4:4 core_select => PeregrineCoreSelect;
- 0:0 valid => bool;
- }
-}
-
// The modules below provide registers that are not identical on all supported chips. They should
// only be used in HAL modules.
--
2.55.0