RE: [PATCH v3 1/6] wifi: rtw88: 8723b: add the RTL8723B register definitions

[Ping-Ke Shih]

Luka Gejak <luka.gejak@xxxxxxxxx> wrote:
> Add the register offsets and bit definitions the RTL8723B driver uses:
> the power and system function bits, the BT antenna and control
> registers, the packet lifetime and MAC ID drop registers, the FPGA0
> HSSI and RF switch control registers, and the RFE antenna path
> registers.
> 
> These are split out from the chip driver so the driver patch that
> follows is easier to read. Nothing references them yet.
> 
> This depends on the shared core handling sent as a separate series,
> "wifi: rtw88: preparations for RTL8723B/RTL8723BS".

No need to point out dependency in commit message. If it is needed,
add it after --- as note. 

But as you have based on rtw/rtw-next, the patchset is merged already.

> 
> Signed-off-by: Luka Gejak <luka.gejak@xxxxxxxxx>

[...]

> @@ -301,6 +308,8 @@
>  #define REG_HMEBOX3            0x01DC
>  #define REG_LLT_INIT           0x01E0
>  #define BIT_LLT_WRITE_ACCESS   BIT(30)
> +#define REG_RFK_FW_ACK_8723B   0x01e7

upper case 0x01E7 as existing ones.

> +#define BIT_RFK_FW_ACK_8723B   BIT(0)
>  #define REG_HMEBOX0_EX         0x01F0
>  #define REG_HMEBOX1_EX         0x01F4
>  #define REG_HMEBOX2_EX         0x01F8

[...]

> @@ -606,12 +624,20 @@
>  #define BIT_RX_PSEL_RST                (BIT(28) | BIT(29))
>  #define REG_TXPSEL             0x080C
>  #define REG_RX_GAIN_EN         0x081c
> +#define REG_FPGA0_XA_HSSI_PARM2        0x0824
> +#define HSSI_3WIRE_ADDR_LEN    0x400
> +#define HSSI_3WIRE_DATA_LEN    0x800
>  #define REG_CCASEL             0x082C
> +#define REG_FPGA0_XB_HSSI_PARM2        0x082c

upper case 0x082C

[...]

> @@ -683,6 +713,7 @@
>  #define REG_RX_IQC_AB_A                0x0c10
>  #define REG_RX_IQC_CD_A                0x0c14
>  #define REG_TXSCALE_A          0x0c1c
> +#define REG_B_RXIQI            0x0c1c

I'd say upper case too, but existing ones are there. Just ignore this. 

>  #define BB_SWING_MASK          GENMASK(31, 21)
>  #define REG_TX_AGC_A_CCK_11_CCK_1              0xc20
>  #define REG_TX_AGC_A_OFDM18_OFDM6              0xc24
> --
> 2.55.0