Re: [PATCH v5 2/2] perf vendor events hygon: Add Hygon Data Fabric PMU events and metrics

From: Qi Liu

Date: Wed Sep 23 2026 - 05:42:45 EST


Hi Sandipan,

Sorry for the delayed reply.

On 8/19/2026 1:11 PM, Sandipan Das wrote:
On 18-08-2026 15:31, Qi Liu wrote:
Add perf JSON event definitions and metrics for the Hygon Data Fabric (DF)
uncore PMU.

Signed-off-by: Qi Liu <liuqi@xxxxxxxx>
---
tools/perf/pmu-events/Build | 2 +-
.../arch/x86/hygonm1/data-fabric.json | 95 ++++++++++
.../arch/x86/hygonm4/data-fabric.json | 134 ++++++++++++++
.../arch/x86/hygonm6/data-fabric.json | 170 ++++++++++++++++++
tools/perf/pmu-events/arch/x86/mapfile.csv | 3 +
tools/perf/pmu-events/jevents.py | 2 +
6 files changed, 405 insertions(+), 1 deletion(-)
create mode 100644 tools/perf/pmu-events/arch/x86/hygonm1/data-fabric.json
create mode 100644 tools/perf/pmu-events/arch/x86/hygonm4/data-fabric.json
create mode 100644 tools/perf/pmu-events/arch/x86/hygonm6/data-fabric.json

diff --git a/tools/perf/pmu-events/Build b/tools/perf/pmu-events/Build
index 372773b998e4..79a9b4cad202 100644
--- a/tools/perf/pmu-events/Build
+++ b/tools/perf/pmu-events/Build
@@ -95,7 +95,7 @@ endif
ifeq ($(JEVENTS_ARCH),$(filter $(JEVENTS_ARCH),x86 all))
# Generate Intel Json
-INTELS := $(shell ls -d pmu-events/arch/x86/*|grep -v amdzen|grep -v mapfile.csv)
+INTELS := $(shell ls -d pmu-events/arch/x86/*|grep -v amdzen|grep -v hygon|grep -v mapfile.csv)
INTEL_METRICS = $(foreach x,$(INTELS),$(OUTPUT)$(x)/extra-metrics.json)
INTEL_METRICGROUPS = $(foreach x,$(INTELS),$(OUTPUT)$(x)/extra-metricgroups.json)
GEN_JSON += $(INTEL_METRICS) $(INTEL_METRICGROUPS)
diff --git a/tools/perf/pmu-events/arch/x86/hygonm1/data-fabric.json b/tools/perf/pmu-events/arch/x86/hygonm1/data-fabric.json
new file mode 100644
index 000000000000..8c6a8e9ba9a5
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/hygonm1/data-fabric.json
@@ -0,0 +1,95 @@
+[
+ {
+ "EventName": "cpu_read_requests_cs_0",
+ "BriefDescription": "Number of CPU read requests to memory in 64-byte units for Coherent Subordinate 0 (CS0).",

Coherent Station is the correct term, if you go by the terminology in AMD
PPRs. Since CSes are the interfaces between the data fabric and the memory
controllers (UMCs), it may be better to rephrase the descriptions as read
or write requests to DRAM channel 0..N which are backed by UMC 0..N and
CS 0..N.

Thanks,I will update "Coherent Subordinate" to "Coherent Station".

Yes, CSes provide the interface between the data fabric and UMCs. Since the UMC-to-DRAM-channel topology may vary across platforms, would it be reasonable to avoid referring to DRAM channels in the event descriptions?

I was thinking of wording the description as follows:
"Number of CPU read requests associated with Coherent Station 0 (CS0) and the UMC."


+ "EventCode": "0x2",
+ "UMask": "0x07",
+ "CompId": "0x0",
+ "Unit": "HYGON_DF",
+ "ScaleUnit": "64Bytes"

As the naming suggests, my understanding is that these events count the
number of requests and each request carries a 64-byte payload. Perhaps
the ScaleUnit needs to be factored into the bandwidth metrics instead of
the individual events.


Thanks,I will remove the "64Bytes" ScaleUnit from the individual request
events in v6.

The bandwidth MetricExprs already apply the payload size: * 64 for the
CPU bandwidth and I/O upper-bound metrics, and * 32 for the I/O
lower-bound metric. I plan to retain those conversions in the metrics.

Does that match your suggestion?

Thanks,
Qi