[PATCH RFC 06/15] media: qcom: camss: vfe: Add support for VFE 1190
From: Nihal Kumar Gupta
Date: Wed Sep 23 2026 - 07:10:43 EST
From: Hangxiang Ma <hangxiang.ma@xxxxxxxxxxxxxxxx>
Add support for the Video Front End (VFE) on Hawi SoC. VFE gen4
has support for VFE 1190.
VFE 1190 uses a different bus write master register layout from the
VFE 1080/980 variants: the per-write-master register block has a
0x200 stride based at 0x1000, and several individual registers sit at
different offsets. Parameterize the bus register macros on the VFE
version so the gen4 driver can serve VFE 1080, 980 and 1190.
This change limits Hawi VFE output lines to 3 for now as constrained by
the CAMSS driver framework.
Signed-off-by: Hangxiang Ma <hangxiang.ma@xxxxxxxxxxxxxxxx>
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@xxxxxxxxxxxxxxxx>
---
drivers/media/platform/qcom/camss/camss-vfe-gen4.c | 49 ++++++++++++++--------
drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
2 files changed, 34 insertions(+), 17 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-vfe-gen4.c b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c
index d73d70898710a2127c606ac8459a1d8c747a2f7c..eece3c8698e66d739dd870d79b549dbba8e52ad1 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe-gen4.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c
@@ -13,36 +13,51 @@
#include "camss.h"
#include "camss-vfe.h"
-/* VFE-gen4 Bus Register Base Addresses */
-#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000)
+#define IS_VFE_1190(vfe) ((vfe)->camss->res->version == CAMSS_HAWI)
+
+#define BUS_REG_BASE_1080 (vfe_is_lite(vfe) ? 0x800 : 0x1000)
-#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
+/* VFE-gen4 Bus Register Base Addresses */
+#define BUS_REG_BASE_1190 (0x800)
+#define BUS_REG_BASE (IS_VFE_1190(vfe) ? BUS_REG_BASE_1190 : \
+ BUS_REG_BASE_1080)
+
+#define BUS_REG_OFFSET_1080(n) (0x500 + (n) * 0x100)
+#define BUS_REG_OFFSET_1190(n) (0x1000 + (n) * 0x200)
+#define BUS_REG_OFFSET(n) (IS_VFE_1190(vfe) ? \
+ BUS_REG_OFFSET_1190(n) : \
+ BUS_REG_OFFSET_1080(n))
+
+#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + \
+ (IS_VFE_1190(vfe) ? 0x4 : 0x8))
#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
-#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0x128)
+#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + \
+ (IS_VFE_1190(vfe) ? 0x144 : 0x128))
-#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x500 + (n) * 0x100)
+#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + BUS_REG_OFFSET(n))
#define WM_CFG_EN BIT(0)
#define WM_VIR_FRM_EN BIT(1)
#define WM_CFG_MODE BIT(16)
-#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x504 + (n) * 0x100)
-#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x508 + (n) * 0x100)
-#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x50C + (n) * 0x100)
+#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0x4)
+#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0x8)
+#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0xC)
#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF)
-#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x514 + (n) * 0x100)
+#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0x14)
#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF)
-#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x518 + (n) * 0x100)
+#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0x18)
-#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x530 + (n) * 0x100)
-#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x534 + (n) * 0x100)
+#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0x30)
+#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0x34)
/* VFE lite has no such registers */
-#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x538 + (n) * 0x100)
-#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x53C + (n) * 0x100)
-
-#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x560 + (n) * 0x100)
-#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x564 + (n) * 0x100)
+#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0x38)
+#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + 0x3C)
+#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + \
+ (IS_VFE_1190(vfe) ? 0x64 : 0x60))
+#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + BUS_REG_OFFSET(n) + \
+ (IS_VFE_1190(vfe) ? 0x68 : 0x64))
/*
* IFE write master client IDs
*
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 826ab85a44a14e611ff9918f6c8de40edf483fb8..92dbd59477ad6cfe2d2e7e663397dde0271a5c16 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -353,6 +353,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
case CAMSS_8550:
case CAMSS_8650:
case CAMSS_8775P:
+ case CAMSS_HAWI:
case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
switch (sink_code) {
@@ -2017,6 +2018,7 @@ static int vfe_bpl_align_rdi(struct vfe_device *vfe)
case CAMSS_8550:
case CAMSS_8650:
case CAMSS_8775P:
+ case CAMSS_HAWI:
case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
ret = 16;
--
2.34.1