[PATCH RFC 12/15] arm64: dts: qcom: maili: Add CAMSS and CSIPHY nodes for Maili
From: Nihal Kumar Gupta
Date: Wed Sep 23 2026 - 07:19:15 EST
Maili uses the same CAMSS IP as Hawi with five CSIPHY instances
instead of six. Add CAMSS and CSIPHY nodes reusing the Hawi-compatible
driver.
5 x CSIPHY
3 x TPG
3 x CSID
2 x CSID Lite
3 x IFE
2 x IFE Lite
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/maili.dtsi | 412 ++++++++++++++++++++++++++++++++++++
1 file changed, 412 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/maili.dtsi b/arch/arm64/boot/dts/qcom/maili.dtsi
index fb404d6c3e92ed95ecd01782c389096fae402701..8d5d64a23642cbde51ecb6c7377a5eed355f0d65 100644
--- a/arch/arm64/boot/dts/qcom/maili.dtsi
+++ b/arch/arm64/boot/dts/qcom/maili.dtsi
@@ -537,6 +537,28 @@ smp2p_soccp_in: slave-kernel {
};
};
+ csiphy_mxc_opp_table: opp-table-mxc {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1_1>,
+ <&rpmhpd_opp_low_svs_d1_1>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>,
+ <&rpmhpd_opp_low_svs_d0>;
+ };
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_nom>;
+ };
+ };
+
soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
@@ -4058,6 +4080,396 @@ lpass_ag_noc: interconnect@8f40000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ camss: isp@9253000 {
+ compatible = "qcom,maili-camss", "qcom,hawi-camss";
+
+ reg = <0x0 0x09253000 0x0 0x5e80>,
+ <0x0 0x09263000 0x0 0x5e80>,
+ <0x0 0x09273000 0x0 0x5e80>,
+ <0x0 0x092d3000 0x0 0x3880>,
+ <0x0 0x092e7000 0x0 0x3880>,
+ <0x0 0x093fd000 0x0 0x400>,
+ <0x0 0x093fe000 0x0 0x400>,
+ <0x0 0x093ff000 0x0 0x400>,
+ <0x0 0x09151000 0x0 0x20000>,
+ <0x0 0x09171000 0x0 0x20000>,
+ <0x0 0x09191000 0x0 0x20000>,
+ <0x0 0x092dc000 0x0 0x6800>,
+ <0x0 0x092f0000 0x0 0x6800>;
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csitpg0",
+ "csitpg1",
+ "csitpg2",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_DCD_XO_CLK>,
+ <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TITAN_MNOC_HF_CLK>,
+ <&camcc CAM_CC_TITAN_MNOC_SF_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
+ clock-names = "camnoc_nrt_axi",
+ "camnoc_rt_axi",
+ "camnoc_dcd_xo",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_mnoc_hf",
+ "cpas_mnoc_sf",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe2",
+ "cpas_vfe_lite",
+ "csid",
+ "csid_csiphy_rx",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "qdss_debug_xo";
+
+ interrupts = <GIC_ESPI 665 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 667 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 495 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 669 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 440 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 497 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 500 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 521 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 670 IRQ_TYPE_EDGE_RISING>,
+ <GIC_ESPI 441 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc";
+
+ iommus = <&apps_smmu 0x1800 0x00>;
+
+ power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
+ <&camcc CAM_CC_TFE_1_GDSC>,
+ <&camcc CAM_CC_TFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "top";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ camss_csiphy0_inep: endpoint {
+ remote-endpoint = <&csiphy0_out_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ camss_csiphy1_inep: endpoint {
+ remote-endpoint = <&csiphy1_out_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ camss_csiphy2_inep: endpoint {
+ remote-endpoint = <&csiphy2_out_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ camss_csiphy3_inep: endpoint {
+ remote-endpoint = <&csiphy3_out_ep>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ camss_csiphy4_inep: endpoint {
+ remote-endpoint = <&csiphy4_out_ep>;
+ };
+ };
+ };
+ };
+
+ csiphy0: phy@9523000 {
+ compatible = "qcom,maili-csi2-phy", "qcom,kaanapali-csi2-phy";
+ reg = <0x0 0x09523000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_ESPI 541 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy0_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy0_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy0_inep>;
+ };
+ };
+ };
+ };
+
+ csiphy1: phy@9525000 {
+ compatible = "qcom,maili-csi2-phy", "qcom,kaanapali-csi2-phy";
+ reg = <0x0 0x09525000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_ESPI 542 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy1_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy1_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy1_inep>;
+ };
+ };
+ };
+ };
+
+ csiphy2: phy@9527000 {
+ compatible = "qcom,maili-csi2-phy", "qcom,kaanapali-csi2-phy";
+ reg = <0x0 0x09527000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_ESPI 543 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy2_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy2_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy2_inep>;
+ };
+ };
+ };
+ };
+
+ csiphy3: phy@9529000 {
+ compatible = "qcom,maili-csi2-phy", "qcom,kaanapali-csi2-phy";
+ reg = <0x0 0x09529000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_ESPI 512 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy3_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy3_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy3_inep>;
+ };
+ };
+ };
+ };
+
+ csiphy4: phy@952b000 {
+ compatible = "qcom,maili-csi2-phy", "qcom,kaanapali-csi2-phy";
+ reg = <0x0 0x0952b000 0x0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_ESPI 186 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_mxc_opp_table>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy4_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy4_out_ep: endpoint {
+ remote-endpoint = <&camss_csiphy4_inep>;
+ };
+ };
+ };
+ };
+
camcc: clock-controller@956d000 {
compatible = "qcom,maili-camcc";
reg = <0x0 0x0956d000 0x0 0x80000>;
--
2.34.1