[PATCH RFC 2/3] dt-bindings: clock: amlogic: Add T7 pre-divider clock IDs
From: Jian Hu via B4 Relay
Date: Wed Sep 23 2026 - 07:20:44 EST
From: Jian Hu <jian.hu@xxxxxxxxxxx>
Add clock IDs for the T7 PLL pre-divider clocks. These IDs are
required for the subsequent conversion of the PLL pre-divider
into a standalone divider clock following the PLL framework refactoring.
Signed-off-by: Jian Hu <jian.hu@xxxxxxxxxxx>
---
include/dt-bindings/clock/amlogic,t7-pll-clkc.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
index e2481f2f1163..69c90bc0be0a 100644
--- a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
+++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
@@ -9,20 +9,24 @@
/* GP0 */
#define CLKID_GP0_PLL_DCO 0
#define CLKID_GP0_PLL 1
+#define CLKID_GP0_PREDIV 2
/* GP1 */
#define CLKID_GP1_PLL_DCO 0
#define CLKID_GP1_PLL 1
+#define CLKID_GP1_PREDIV 2
/* HIFI */
#define CLKID_HIFI_PLL_DCO 0
#define CLKID_HIFI_PLL 1
+#define CLKID_HIFI_PREDIV 2
/* PCIE */
#define CLKID_PCIE_PLL_DCO 0
#define CLKID_PCIE_PLL_DCO_DIV2 1
#define CLKID_PCIE_PLL_OD 2
#define CLKID_PCIE_PLL 3
+#define CLKID_PCIE_PREDIV 4
/* MPLL */
#define CLKID_MPLL_PREDIV 0
@@ -39,6 +43,7 @@
#define CLKID_HDMI_PLL_DCO 0
#define CLKID_HDMI_PLL_OD 1
#define CLKID_HDMI_PLL 2
+#define CLKID_HDMI_PREDIV 3
/* MCLK */
#define CLKID_MCLK_PLL_DCO 0
@@ -52,5 +57,6 @@
#define CLKID_MCLK_1_DIV2 8
#define CLKID_MCLK_1_PRE 9
#define CLKID_MCLK_1 10
+#define CLKID_MCLK_PREDIV 11
#endif /* __T7_PLL_CLKC_H */
--
2.47.1