Re: [REGRESSION] Resolutions broken after "drm/msm: dsi: fix PLL init in bonded mode"

[Dmitry Baryshkov]

On Wed, Sep 23, 2026 at 12:48:21PM +0200, neil.armstrong@xxxxxxxxxx wrote:
> Hi,
> 
> On 7/8/26 15:31, Dmitry Baryshkov wrote:
> > On Wed, Jul 08, 2026 at 09:26:04AM +0200, Thorsten Leemhuis wrote:
> > > On 7/6/26 11:52, Mohit Dsor wrote:
> > > > On Wed, Jun 03, 2026 at 03:11:34PM +0300, Dmitry Baryshkov wrote:
> > > > > On Wed, Jun 03, 2026 at 11:56:15AM +0200, Thorsten Leemhuis wrote:
> > > > > > On 5/4/26 22:09, Mohit Dsor wrote:
> > > > > > > Sorry for the late reply. I am attaching clk_summary and reg_dump in
> > > > > > > working and non working case. Lilliput is just a normal display working
> > > > > > > with hdmi and has 720p as preferred mode. Yes, I was talking about RB3
> > > > > > > Gen2 only.
> > > > > > 
> > > > > > Neil, Dmitry, and Mohit: what's the status here? From the outside it
> > > > > > looks like this regression is still unfixed with nothing happening for
> > > > > > weeks now. Or has progress been made and I just missed it?
> > > > > 
> > > > > Thanks as a reminder. Unfortunately, it takes some more time (and I've
> > > > > been a bit overloaded lately). Worst case I will send a revert soon.
> > > > > 
> > > > Just wanted to check if you had a chance to look into this issue and whether there's any update on the investigation from your side.
> > > Hmm, no reply. Given that we are entering holiday season and are way
> > > past what Linus expects in a situation like this[1] I'd say we should go
> > > for a revert, unless some fix shows up really soon now.
> 
> Sorry I'm very late to the party, and checked again, reverting this breaks all dual-DSI setup
> on SM8650, and probably other similar SoCs.
> 
> Here's a complete log of the breakage which appears on the Ayaneo PS2 running v7.3-rc3 with mainline panel driver: https://gitlab.postmarketos.org/-/snippets/65
> 
> I don't see why my fix did break this use case since it reverted the way the dual DSI PHYs
> were initialized to actually allow the dual-DSI setup.

See commit cb55f39bf7b1. Without PLL_SHUTDOWNB and DIGTOP_PWRDN_B most
of the PLL registers read as zero. Currently the regs are handled
correctly (almost). With your patch in place the SHUTDOWNB gets dropped,
making PLL loose reg contents (and return 0 to CCF as the selected divisor).
Current code depends on those two bits being set across host_power_on.

> 
> Thanks,
> Neil
> 
> > > 
> > > Ciao, Thorsten
> > 
> > Please send a revert.
> > 
> > > 
> > > [1] To quote Linus statements from
> > > https://www.kernel.org/doc/html/latest/process/handling-regressions.html#on-how-quickly-regressions-should-be-fixed
> > > 
> > > """
> > >  From 2026-01-22:
> > > 
> > >   But a user complaining should basically result in an immediate fix -
> > >   possibly a "revert and rethink".
> > > 
> > > With a later clarification on 2026-01-28:
> > > 
> > >   It's also worth noting that "immediate" obviously doesn't mean "right
> > >   this *second* when the problem has been reported".
> > > 
> > >   But if it's a regression with a known commit that caused it, I think
> > >   the rule of thumb should generally be "within a week", preferably
> > >   before the next rc.
> > > """
> > 
> 

-- 
With best wishes
Dmitry