Re: [PATCH Intenal 2/2] EDAC/amd64: Limit UMC csrow decode to the implemented chip selects

[Yazen Ghannam]

On Wed, Sep 23, 2026 at 04:50:03PM +0530, Vishal Badole wrote:
> For DRAM ECC errors on SMCA systems, the Chip Select which reported the
> error is encoded in the MCA_SYND[ErrorInformation] field. The EDAC core
> uses that value to index into the csrow array which was sized during
> probe from pvt->csels[].b_cnt.
> 
> On Family 1Ah Model 88h a corrected DRAM error results in:
> 
>   EDAC MC0: INTERNAL ERROR: csrow value is out of range (5 >= 4)
>   WARNING: drivers/edac/edac_mc.c:919 at edac_raw_mc_handle_error
> 
> and the error is subsequently reported against "unknown memory", so the
> DIMM which actually reported the error cannot be identified.
> 
> This happens because the syndrome field is masked with a hardcoded 0x7,
> i.e. eight possible chip selects, while umc_prep_chip_selects() sizes
> every UMC channel for four. Bit 2 of that field is therefore not a valid
> Chip Select bit, and whenever hardware leaves it set the decoded value
> exceeds the number of csrows the EDAC core knows about.

This isn't an accurate description of the issue.

For this model, the hardcoded 0x7 mask is correct. The register
definition shows "MCA_SYND_UMC[2:0] = Chip Select" for this error code.

The issue is that some forms of error 'injection' populate the registers
with hardcoded values that don't necessarily reflect the hardware.

> 
> Mask with the number of chip selects the controller actually implements
> so the decoded value can never exceed what was allocated, instead of
> relying on an assumption about the field width that no longer holds.
> 

In practice, the simpler solution is to change the mask to 0x3.
Documentation for newer products show "MCA_SYND_UMC[1:0] = Chip Select".
And older products only ever had 4 chip selects as you point out.

Thanks,
Yazen