[PATCH 0/3] qcom: videocc: Fix sleep clock on Glymur/SM8750

[Shawn Guo]

videocc-glymur.c (qcom,glymur-videocc, qcom,nord-videocc) and
videocc-sm8750.c both declare three DT clock inputs, DT_BI_TCXO,
DT_BI_TCXO_AO and DT_SLEEP_CLK, and parent video_cc_sleep_clk_src on
DT_SLEEP_CLK.

qcom,sm8450-videocc.yaml, which covers both drivers, documents exactly
two inputs: a board XO and a video AHB clock from GCC. No device tree
can therefore supply the third input, and video_cc_sleep_clk_src can
never resolve its parent. It registers as an orphan clock:
clk_set_rate() on it fails, and it appears parentless in clk_summary.

Nothing breaks at runtime today, for two reasons worth recording:
qcom_cc_probe() does not fail on an unresolved parent_data.index, it
just orphans the clock; and VIDEO_CC_SLEEP_CLK (0x8138) is listed in
the critical CBCRs of both drivers, so the branch is force enabled
through regmap and bypasses the clock framework entirely. The sleep
source keeps whatever rate the bootloader programmed. The orphan still
blocks any future rate management of the video sleep path.

The two-input description is not wrong for every compatible in that
schema. videocc-hawi.c, videocc-kaanapali.c and videocc-maili.c really
do take DT_BI_TCXO and DT_AHB_CLK, and sm8450/sm8550/x1p42100 never
resolve index 1 at all. So this series narrows the description per
compatible rather than changing it for everyone:

  - patch 1 lets the Glymur, Nord and SM8750 compatibles take three
    inputs, described as board XO, board always-on XO and sleep clock,
    and leaves the rest at two.
  - patch 2 adds the sleep clock to the Glymur videocc node.
  - patch 3 does the same for SM8750, and also moves its second input
    from GCC_VIDEO_AHB_CLK to bi_tcxo_ao_div2, which is what the driver
    expects at that index.

The sibling qcom,glymur-evacc.yaml on the same SoC is the precedent:
evacc-glymur.c has the same shape, its schema documents a sleep clock,
and the glymur evacc node already passes one.

The Glymur and SM8750 changes are not tested on those boards. The
equivalent change was verified on Nord, which binds the same
videocc-glymur.c: before it, video_cc_sleep_clk_src appears in
/sys/kernel/debug/clk/clk_orphan_summary; after it, the orphan is gone
and the RCG is parented to the board sleep clock at 32 kHz. The SM8750
change is by inspection of videocc-sm8750.c, which declares the same
three DT inputs. Both should be runtime no-ops otherwise, since the
sleep branch is force enabled as a critical CBCR and index 1 is not
resolved by either driver.

Shawn Guo (3):
  dt-bindings: clock: qcom,sm8450-videocc: Fix clock inputs for Glymur
  arm64: dts: qcom: glymur: Add videocc sleep clock
  arm64: dts: qcom: sm8750: Fix videocc clock inputs

 .../bindings/clock/qcom,sm8450-videocc.yaml   | 26 ++++++++++++++++---
 arch/arm64/boot/dts/qcom/glymur.dtsi          |  3 ++-
 arch/arm64/boot/dts/qcom/sm8750.dtsi          |  3 ++-
 3 files changed, 27 insertions(+), 5 deletions(-)

-- 
2.43.0