Re: [PATCH v4 7/8] ASoC: qcom: lpass-tx-macro: Add support for Bolero v4.0
From: Ajay Kumar Nandam
Date: Fri Sep 25 2026 - 06:23:01 EST
On 9/22/2026 3:12 PM, Mohammad Rafi Shaik wrote:
From: Prasad Kumpatla <prasad.kumpatla@xxxxxxxxxxxxxxxx>
Hawi integrates the Bolero v4.0 TX macro, which extends the v9.x TX
macro with a port-select stage in the SWR microphone input path and an
adaptive filter (ADPT) block.
Add the additional CFG2 mux registers and per-path CFG2 registers to the
register map, extend the maximum register offset to cover the new ADPT
control register, and describe the new v4.0 decimator, SWR microphone,
WSA and port-select mux widgets and their routes.
The ADPT block has to be disabled before a decimator is enabled. This
register only exists on v4.0, so gate the write on a has_adpt flag set
from the match data rather than issuing it unconditionally.
Add the "qcom,hawi-lpass-tx-macro" compatible and its match data to
select the new widgets and routes.
Co-developed-by: Sarath Ganapathiraju <sarath.ganapathiraju@xxxxxxxxxxxxxxxx>
Signed-off-by: Sarath Ganapathiraju <sarath.ganapathiraju@xxxxxxxxxxxxxxxx>
Signed-off-by: Prasad Kumpatla <prasad.kumpatla@xxxxxxxxxxxxxxxx>
Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@xxxxxxxxxxxxxxxx>
---
sound/soc/codecs/lpass-macro-common.h | 1 +
sound/soc/codecs/lpass-tx-macro.c | 442 +++++++++++++++++++++++++++++++++-
2 files changed, 442 insertions(+), 1 deletion(-)
diff --git a/sound/soc/codecs/lpass-macro-common.h b/sound/soc/codecs/lpass-macro-common.h
index b52665b11e35..707b22a6bda6 100644
--- a/sound/soc/codecs/lpass-macro-common.h
+++ b/sound/soc/codecs/lpass-macro-common.h
@@ -16,6 +16,7 @@ enum lpass_version {
LPASS_VER_9_2_0,
LPASS_VER_10_0_0,
LPASS_VER_11_0_0,
+ LPASS_VER_15_0_0,
};
enum lpass_codec_version {
diff --git a/sound/soc/codecs/lpass-tx-macro.c b/sound/soc/codecs/lpass-tx-macro.c
index 6deaaabe43af..b1eee16e968c 100644
--- a/sound/soc/codecs/lpass-tx-macro.c
+++ b/sound/soc/codecs/lpass-tx-macro.c
@@ -67,6 +67,14 @@
#define CDC_TX_INP_MUX_ADC_MUX6_CFG1 (0x0134)
#define CDC_TX_INP_MUX_ADC_MUX7_CFG0 (0x0138)
#define CDC_TX_INP_MUX_ADC_MUX7_CFG1 (0x013C)
+#define CDC_TX_INP_MUX_ADC_MUX0_CFG2 (0x0140)
+#define CDC_TX_INP_MUX_ADC_MUX1_CFG2 (0x0144)
+#define CDC_TX_INP_MUX_ADC_MUX2_CFG2 (0x0148)
+#define CDC_TX_INP_MUX_ADC_MUX3_CFG2 (0x014C)
+#define CDC_TX_INP_MUX_ADC_MUX4_CFG2 (0x0150)
+#define CDC_TX_INP_MUX_ADC_MUX5_CFG2 (0x0154)
+#define CDC_TX_INP_MUX_ADC_MUX6_CFG2 (0x0158)
+#define CDC_TX_INP_MUX_ADC_MUX7_CFG2 (0x015C)
#define CDC_TX_ANC0_CLK_RESET_CTL (0x0200)
#define CDC_TX_ANC0_MODE_1_CTL (0x0204)
#define CDC_TX_ANC0_MODE_2_CTL (0x0208)
@@ -108,6 +116,16 @@
#define CDC_TX0_TX_PATH_SEC5 (0x0424)
#define CDC_TX0_TX_PATH_SEC6 (0x0428)
#define CDC_TX0_TX_PATH_SEC7 (0x042C)
+#define CDC_TX0_TX_PATH_CFG2 (0x0430)
+#define CDC_TX1_TX_PATH_CFG2 (0x04B0)
+#define CDC_TX2_TX_PATH_CFG2 (0x0530)
+#define CDC_TX3_TX_PATH_CFG2 (0x05B0)
+#define CDC_TX4_TX_PATH_CFG2 (0x0630)
+#define CDC_TX5_TX_PATH_CFG2 (0x06B0)
+#define CDC_TX6_TX_PATH_CFG2 (0x0730)
+#define CDC_TX7_TX_PATH_CFG2 (0x07B0)
+#define CDC_ADPT0_ADPT_CTRL (0x0800)
+
#define CDC_TX0_MBHC_CTL_EN_MASK BIT(6)
#define CDC_TX1_TX_PATH_CTL (0x0480)
#define CDC_TX1_TX_PATH_CFG0 (0x0484)
@@ -186,7 +204,7 @@
#define CDC_TX7_TX_PATH_SEC4 (0x07A0)
#define CDC_TX7_TX_PATH_SEC5 (0x07A4)
#define CDC_TX7_TX_PATH_SEC6 (0x07A8)
-#define TX_MAX_OFFSET (0x07A8)
+#define TX_MAX_OFFSET (CDC_ADPT0_ADPT_CTRL)
These registers look v4.0-specific from the commit message, but TX_MAX_OFFSET, tx_defaults[] and tx_is_rw_register() are updated in the shared regmap configuration used by all TX macro variants.
The explicit CDC_ADPT0_ADPT_CTRL write is gated with has_adpt, but regcache_sync() can still sync the new default registers on older non-v4.0 hardware because the regmap config/default table is shared.
Should this use a v4.0-specific regmap_config/default table, similar to the VA macro, or are the CFG2/ADPT registers guaranteed to be harmless/present on all TX macro variants?
#define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\