Re: [PATCH v3 13/19] clk: starfive: jh7110-vout: Allow pixel clock rate propagation

[Icenowy Zheng]

在 2026-09-25五的 14:47 +0200，Jerome Brunet写道：
> On ven. 04 sept. 2026 at 15:27, Michal Wilczynski
> <m.wilczynski@xxxxxxxxxxx> wrote:
> 
> > The dc8200_pix0 and dc8200_pix1 MUXes feed the display controller,
> > and
> > the rate they carry is ultimately produced by the HDMI PHY, which
> > registers hdmitx0_pixelclk as a clock provider.
> > 
> > Add CLK_SET_RATE_PARENT to both MUXes so a rate requested on them
> > reaches that parent, instead of being clamped to whatever rate the
> > parent already happens to run at.
> > 
> > Co-developed-by: Dominique Belhachemi <db@xxxxxxxxxx>
> > Signed-off-by: Dominique Belhachemi <db@xxxxxxxxxx>
> > Signed-off-by: Michal Wilczynski <m.wilczynski@xxxxxxxxxxx>
> > ---
> >  drivers/clk/starfive/clk-starfive-jh7110-vout.c | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c
> > b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
> > index
> > bad20d5d794a72f071b4d547b7304786a8ba9afa..aeba42cd3c44ba205ced52b18
> > 26d2d2de82ad78f 100644
> > --- a/drivers/clk/starfive/clk-starfive-jh7110-vout.c
> > +++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
> > @@ -40,10 +40,12 @@ static const struct jh71x0_clk_data
> > jh7110_voutclk_data[] = {
> >  	JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0,
> > JH7110_VOUTCLK_VOUT_TOP_AXI),
> >  	JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0,
> > JH7110_VOUTCLK_VOUT_TOP_AXI),
> >  	JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0,
> > JH7110_VOUTCLK_VOUT_TOP_AHB),
> > -	JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0,
> > 2,
> > +	JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0",
> > +		    CLK_SET_RATE_PARENT |
> > CLK_SET_RATE_NO_REPARENT, 2,
> 
> I see that you've added CLK_SET_RATE_NO_REPARENT following a previous
> sashiko advice.

I think the problem is that the Innosilicon HDMI PHY is designed to be
solely the pixel clock provider when HDMI output is enabled, so manual
clock parent assginment is required when using HDMI to prevent the
general PLL from driving the pixel clock, and for DSI to prevent
abusing the HDMI PHY clock generator.

Thanks,
Icenowy

> 
> Note that saying it will 'hijack' the parent without it is kind of
> strong. It is fine to let a mux reparent while setting a rate, as
> long
> as you understand the possible consequences for the rest of the tree.
> 
> Regardless
> 
> Reviewed-by: Jerome Brunet <jbrunet@xxxxxxxxxxxx>
> 
> >  		    JH7110_VOUTCLK_DC8200_PIX,
> >  		    JH7110_VOUTCLK_HDMITX0_PIXELCLK),
> > -	JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0,
> > 2,
> > +	JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1",
> > +		    CLK_SET_RATE_PARENT |
> > CLK_SET_RATE_NO_REPARENT, 2,
> >  		    JH7110_VOUTCLK_DC8200_PIX,
> >  		    JH7110_VOUTCLK_HDMITX0_PIXELCLK),
> >  	/* LCD */
> > 
> > -- 
> > 2.34.1
> >