Re: [PATCH] clk: qcom: mmcc-sdm660: Fix MDSS AHB clock HWCG register offset

[Bjorn Andersson]

On Wed, 16 Sep 2026 14:55:46 +0300, Abel Vesa wrote:
> The MDSS AHB clock HWCG bit resides in the same register as the branch
> enable and halt status bits, at offset 0x2308. The current HWCG register
> offset of 0x8a004 exceeds the regmap maximum of 0x40000, so regmap rejects
> the read in clk_branch_in_hwcg_mode(). Since the read error is ignored,
> the helper uses an uninitialized value to decide whether to skip the
> halt status check.
> 
> [...]

Applied, thanks!

[1/1] clk: qcom: mmcc-sdm660: Fix MDSS AHB clock HWCG register offset
      commit: dd867967e612719cc8c7a20065f03ae4ab4663ca

Best regards,
-- 
Bjorn Andersson <andersson@xxxxxxxxxx>