Re: [PATCH] clk: qcom: gcc: Fix GPLL enable register offset for Nord SoC

[Bjorn Andersson]

On Thu, 24 Sep 2026 15:09:56 +0530, Taniya Das wrote:
> The GPLLs in the North-East, North-West and South-East global clock
> controllers on the Qualcomm Nord SoC were registered with a placeholder
> enable register offset of 0x0. As a result the shared PLL voting register
> was never programmed, leaving the PLLs' enable state uncontrolled.
> 
> Point each GPLL at its actual GPLL_ENABLE register (0x57010 for the
> North-East and South-East controllers, 0x76008 for the North-West
> controller). Each PLL continues to select its own vote bit through
> enable_mask.
> 
> [...]

Applied, thanks!

[1/1] clk: qcom: gcc: Fix GPLL enable register offset for Nord SoC
      commit: a032e3f9c241b9c148f6ef235df8adc8db61eb29

Best regards,
-- 
Bjorn Andersson <andersson@xxxxxxxxxx>