Re: [PATCH 3/5] MIPS: OCTEON: read the L2 crippled fuses from MIO_FUS_DAT3 on OCTEON II
From: Thomas Bogendoerfer
Date: Sat Sep 26 2026 - 06:28:53 EST
On Tue, Sep 15, 2026 at 07:12:46AM +0000, Orgad Shaneh wrote:
> prom_init() decides whether to lock lines into the L2 by reading
> L2D_FUS3, a CN3XXX/CN5XXX register. On OCTEON II the fuses that cripple
> the L2 are MIO_FUS_DAT3[l2c_crip] - which is what cvmx_l2c_get_num_assoc()
> already reads for those parts - so the test looks at an address that is
> not a register on the chip and gets a meaningless answer: it can skip
> L2 locking on a healthy cache, or lock into a reduced one.
>
> Pick the register by family in a small helper.
>
> Assisted-by: Claude:claude-opus-5
> Signed-off-by: Orgad Shaneh <orgads@xxxxxxxxx>
> ---
> diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
> --- a/arch/mips/cavium-octeon/setup.c
> +++ b/arch/mips/cavium-octeon/setup.c
> @@ -653,6 +653,24 @@ void octeon_user_io_init(void)
> write_c0_derraddr1(0);
> }
>
> +#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
> +static bool __init octeon_l2_is_crippled(void)
> +{
> + /*
> + * L2D_FUS3 exists on CN3XXX/CN5XXX only. On OCTEON II the
> + * crippled-L2 fuses live in MIO_FUS_DAT3[l2c_crip].
> + */
> + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
> + union cvmx_mio_fus_dat3 fus_dat3;
> +
> + fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
> + return fus_dat3.s.l2c_crip != 0;
> + }
> +
> + return cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34);
> +}
> +#endif
> +
> /**
> * prom_init - Early entry point for arch setup
> */
> @@ -801,7 +819,7 @@ void __init prom_init(void)
> }
>
> #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
> - if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
> + if (octeon_l2_is_crippled()) {
> pr_info("Skipping L2 locking due to reduced L2 cache size\n");
> } else {
> uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000;
> --
> 2.47.0
applied to mips-next
Thomas.
--
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good idea. [ RFC1925, 2.3 ]