Re: [PATCH 1/4] mmc: sdhci-cadence6: add PHY settle delay after tuning DLL re-lock

[Kathpalia, Tanmay]

On 22-09-2026 16:42, tze.yee.ng@xxxxxxxxxx wrote:
> From: Tze Yee Ng<tze.yee.ng@xxxxxxxxxx>
>
> After re-locking the DLL, allow the same 5 to 5.5 ms for the clock and
> PHY signals to stabilize as sdhci_cdns6_phy_init() does. Without this
> settle time the command issued immediately after tuning (e.g. the R1b
> CMD6 that switches eMMC from HS200 down to HS during HS400 selection)
> can time out.

One additional concern is that the testing listed in the cover letter 
does not
exercise the paths described here. The series reports testing SD DDR50 
and eMMC
DDR52, but neither mode performs tuning through sdhci_cdns6_set_tune_val().

Please test this change with eMMC HS200 and HS400. The same function is also
used during SD SDR104 tuning, so SDR104 should be covered as well.