Re: [PATCH v4 7/8] clk: sunxi-ng: a733: Add bus clock gates
From: Enzo Adriano
Date: Sat Sep 26 2026 - 17:02:40 EST
Hi Junhui,
Attached are the exact minimal board DTS and SoC DTSI used for both runs,
plus the configuration extracted from the tested Image and reproduction
notes. I rebuilt the DTB from the recorded source and recovered config;
it matches the tested 4497-byte DTB byte-for-byte (SHA-256):
4c7b762757392334e8b7ac525e60bf5757ec23b34efdcc949d2093c238b1ed16
The support archive contains the two local integration/comparator diffs,
the four A733 clock/reset headers, source history and short UART excerpts.
Applying the 19 published patches and these local diffs to v7.3-rc1
reproduces the tested source tree. This is the minimal diagnostic DT,
not my newer DTS work; its fixed card supply is part of that test setup.
Both the September 21 failing run and September 26 clk_ignore_unused run
report identical firmware banners:
U-Boot 2018.07-12-boot-aw2501-gb2d229198b2-dirty
(Jan 06 2026 - 03:45:33 +0000) Allwinner Technology
BL31: v2.5(debug):5fc237a6a
BL31: Built : 09:05:28, Feb 26 2025
These tests used the vendor firmware already installed on the A7S;
I did not build or flash U-Boot or TF-A for them. Unfortunately, I cannot
establish the original installation/download image, the U-Boot dirty
delta, or the BL31 source/build inputs. I also do not have verified hashes
of the installed firmware binaries. Earlier source-correlation records
point to Radxa's downstream U-Boot, but the retained candidate build is
a different revision and is not a reproducible source for this firmware.
reproduce.txt includes the actual ext4load/booti commands and bootargs.
In particular, I set the U-Boot environment variable drm_debug=1 as well
as including it in bootargs. U-Boot reports FDT fixup errors and "update
dts" before Linux, also on the successful run; the excerpts retain those
messages. The DTB hash above describes the file loaded into RAM. I did
not capture the final post-fixup tree passed to Linux, so I cannot yet
rule out a firmware or DT-fixup difference from your A7A.
Assisted-by: Codex:gpt-6
Regards,
Enzo
// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
/dts-v1/;
#include "sun60i-a733.dtsi"
/ {
model = "Radxa Cubie A7S";
compatible = "radxa,cubie-a7s", "allwinner,sun60i-a733";
aliases {
serial0 = &uart0;
mmc0 = &mmc0;
};
chosen {
stdout-path = "serial0:115200n8";
};
hosc: hosc-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "hosc";
};
reg_vcc3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
no-mmc;
no-sdio;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb9_pb10_pins>;
status = "okay";
};
// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/allwinner,sun60i-a733-ccu.h>
#include <dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/reset/allwinner,sun60i-a733-ccu.h>
#include <dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x000>;
enable-method = "psci";
capacity-dmips-mhz = <530>;
};
cpu1: cpu@100 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x100>;
enable-method = "psci";
capacity-dmips-mhz = <530>;
};
cpu2: cpu@200 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x200>;
enable-method = "psci";
capacity-dmips-mhz = <530>;
};
cpu3: cpu@300 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x300>;
enable-method = "psci";
capacity-dmips-mhz = <530>;
};
cpu4: cpu@400 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x400>;
enable-method = "psci";
capacity-dmips-mhz = <530>;
};
cpu5: cpu@500 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x500>;
enable-method = "psci";
capacity-dmips-mhz = <530>;
};
cpu6: cpu@600 {
compatible = "arm,cortex-a76";
device_type = "cpu";
reg = <0x600>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
};
cpu7: cpu@700 {
compatible = "arm,cortex-a76";
device_type = "cpu";
reg = <0x700>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
arm,no-tick-in-suspend;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x40000000>;
pio: pinctrl@2000000 {
compatible = "allwinner,sun60i-a733-pinctrl";
reg = <0x02000000 0x600>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB1>, <&hosc>, <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
allwinner,pinmux = <2>;
function = "mmc0";
drive-strength = <30>;
bias-pull-up;
};
uart0_pb9_pb10_pins: uart0-pb9-pb10-pins {
pins = "PB9", "PB10";
allwinner,pinmux = <2>;
function = "uart0";
};
};
ccu: clock-controller@2002000 {
compatible = "allwinner,sun60i-a733-ccu";
reg = <0x02002000 0x2000>;
clocks = <&hosc>, <&rtc CLK_OSC32K>,
<&rtc CLK_IOSC>, <&rtc CLK_OSC32K_FANOUT>;
clock-names = "hosc", "losc", "iosc", "losc-fanout";
#clock-cells = <1>;
#reset-cells = <1>;
};
uart0: serial@2500000 {
compatible = "snps,dw-apb-uart";
reg = <0x02500000 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART0>;
resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
gic: interrupt-controller@3400000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x03400000 0x10000>,
<0x03460000 0x100000>;
};
mmc0: mmc@4020000 {
compatible = "allwinner,sun60i-a733-mmc",
"allwinner,sun20i-d1-mmc";
reg = <0x04020000 0x1000>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
max-frequency = <200000000>;
cap-sd-highspeed;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
r_ccu: clock-controller@7010000 {
compatible = "allwinner,sun60i-a733-r-ccu";
reg = <0x07010000 0x230>;
clocks = <&hosc>, <&rtc CLK_OSC32K>,
<&rtc CLK_IOSC>, <&ccu CLK_SYS_24M>,
<&ccu CLK_PLL_PERIPH0_200M>,
<&ccu CLK_PLL_PERIPH0_300M>,
<&ccu CLK_PLL_PERIPH1_300M>;
clock-names = "hosc", "losc", "iosc", "sys-24m",
"pll-periph0-200m", "pll-periph0-300m",
"pll-periph1-300m";
#clock-cells = <1>;
#reset-cells = <1>;
};
rtc: rtc@7090000 {
compatible = "allwinner,sun60i-a733-rtc",
"allwinner,sun50i-r329-rtc";
reg = <0x07090000 0x400>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_BUS_R_RTC>, <&hosc>,
<&r_ccu CLK_R_AHB>;
clock-names = "bus", "hosc", "ahb";
#clock-cells = <1>;
};
};
};
Exact minimal DT used for the CCU v4 A7S diagnostic
==================================================
This is the small test DT, NOT the newer private DTS v2. The board explicitly enables
UART0 and MMC0. It retains the fixed 3.3 V card supply
used for this diagnostic, not a validated PMIC/card supply description.
Base: v7.3-rc1, cee9395acd8043be0644b25c34bfa86623f2b935.
Local tested source head: 937756dcfb9fd853c91269c45d106026cca26607.
Local commit hashes are recorded for identity, not advertised as public refs.
Reconstruct in a disposable Linux checkout at that base:
1. Apply the four single-divider patches:
https://lore.kernel.org/all/20260906-sunxi-clk-no-p-v1-0-cbde21c9fe69@xxxxxxxxxxxxx/
2. Apply all eight CCU v4 patches:
https://lore.kernel.org/all/20260921-a733-clk-v4-0-9c184ebe9ac1@xxxxxxxxxxxxx/
3. Apply minimal-dt-integration.diff from reproduction-support.tar.gz.
This includes the board binding, Makefile entry and the two attached DT
sources, using the CCU v4 binding header names.
4. Apply all seven pinctrl patches:
https://lore.kernel.org/all/20260910133519.459011-1-andre.przywara@xxxxxxx/
5. Apply ahb-cpus-comparator.diff. This is the one-line CLK_IS_CRITICAL
diagnostic change, not a submitted fix.
The support archive also contains the four A733 clock/reset binding headers
from the exact tested commit. Compare them with those installed by CCU v4;
do not replace them with a newer version. arm-gic.h, irq.h and sun6i-rtc.h
are supplied by the base tree. source-history.txt records all local commits.
Use b4 am to retrieve each series and git am to apply its resulting mailbox.
Apply the two local diff files with git apply. Then, from the checkout:
mkdir -p ../a733-test-build
gzip -dc /path/to/tested.config.gz > ../a733-test-build/.config
make O=../a733-test-build ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- olddefconfig
make O=../a733-test-build ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- -j8 allwinner/sun60i-a733-cubie-a7s.dtb
The configuration was extracted from the exact tested Image with
scripts/extract-ikconfig, not copied from a later tracing build directory.
Compiler recorded in that Image/config: aarch64-linux-gnu-gcc
(Ubuntu 15.2.0-16ubuntu1) 15.2.0; binutils banner: 2.46.
The isolated DTB rebuild matches the original, size 4497 bytes, SHA256:
4c7b762757392334e8b7ac525e60bf5757ec23b34efdcc949d2093c238b1ed16
Original payloads (not attached):
Image, 42928640 bytes:
14d1415a80258170616f97e5b55e1b8d3dac4f9d67d4d870a0582e5e569a0f63
initramfs.cpio.gz, 5680294 bytes:
37675cf26adc7b1a1ab8f9e1d6613523b561149ec4b7c710c877d9bf352b8db0
The userspace is an initramfs /bin/sh smoke harness. These instructions
reproduce the DT; no byte-identical rebuilt Image or initramfs is claimed.
Boot commands and firmware caveat
-------------------------------
The successful run loaded from the existing vendor eMMC filesystem using
ext4load mmc 0:3, directly into RAM. No firmware was flashed for these tests.
The recorded staging directory was
/home/radxa/a733-ccu-v4-clk-ignore-unused-r2-20260926.
Commands below preserve the recorded arguments and payload CRC checks:
setenv drm_debug 1
setenv kernel_addr_r 0x40080000
setenv ramdisk_addr_r 0x4c000000
setenv fdt_addr_r 0x4fa00000
setenv bootargs console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x02500000 loglevel=8 ignore_loglevel drm_debug=1 ro rootflags=noload rdinit=/bin/sh init=/bin/sh clk_ignore_unused
ext4load mmc 0:3 0x40080000 /home/radxa/a733-ccu-v4-clk-ignore-unused-r2-20260926/Image
crc32 0x40080000 0x28f0a00
ext4load mmc 0:3 0x4c000000 /home/radxa/a733-ccu-v4-clk-ignore-unused-r2-20260926/initramfs.cpio.gz
crc32 0x4c000000 0x56aca6
ext4load mmc 0:3 0x4fa00000 /home/radxa/a733-ccu-v4-clk-ignore-unused-r2-20260926/sun60i-a733-cubie-a7s.dtb
crc32 0x4fa00000 0x1191
fdt addr 0x4fa00000
booti 0x40080000 0x4c000000:0x56aca6 0x4fa00000
Expected CRCs: Image 3449b907; initramfs 2bc19206; DTB 3fe3901c.
For the earlier failing comparator, clk_ignore_unused was absent; payload
bytes were identical. Staging directory differed. No saveenv was issued.
The drm_debug environment variable was set separately from bootargs.
Both UART captures show the same U-Boot and BL31 version/build banners;
see the two excerpts in the support archive. U-Boot reports FDT fixup errors
and "update dts" before Linux, including in the successful run. The attached
DT sources/hash identify the file loaded into RAM, not an asserted exact
post-fixup DT presented to Linux. No final flattened DT dump was captured.
No claim is made that U-Boot's fixups are identical to those on the A7A.
Firmware origin
---------------
These runs used the vendor firmware already installed on this A7S.
U-Boot: 2018.07-12-boot-aw2501-gb2d229198b2-dirty
Jan 06 2026 - 03:45:33 +0000, Allwinner Technology
BL31: v2.5(debug):5fc237a6a
Built: 09:05:28, Feb 26 2025
I cannot identify the original download/installation image or provide a
verified installed-binary hash. The installation history is unknown.
Earlier local source-correlation records associate the U-Boot banner with
Radxa's downstream U-Boot repository, but this does not identify its dirty
changes or reproduce the installed bytes. The retained candidate U-Boot
build in those records has a different revision (8f59d3cea4d). The BL31
source repository and build inputs remain unknown. No nearby firmware binary
is supplied or represented as the firmware used by these tests.
Attachment:
tested.config.gz
Description: application/gzip
Attachment:
reproduction-support.tar.gz
Description: application/gzip