Re: [PATCH v5 6/6] drm/panel: Add driver for Synaptics R63455 DSI panel

[Linus Walleij]

Hi Jun,

thanks for your patch!

On Mon, Jul 27, 2026 at 10:09 AM Jun Nie <jun.nie@xxxxxxxxxx> wrote:

> +#define R63455_MF_CMD_ACCESS_PROTECT   0xb0
> +#define R63455_SEQ_CTL                 0xd6
> +#define R63455_DSI_CTL                 0xb6
> +#define R63455_DISP_MODE               0xb7
> +#define R63455_GEN_OUTPIN_SET          0xb9
> +#define R63455_DISP_SET1               0xc0
> +#define R63455_DISP_SET2               0xf1
> +#define R63455_DISP_SET3               0xc6
> +#define R63455_DISP_SET3_2             0xcd
> +#define R63455_DISP_SET4               0xcf
> +#define R63455_DISP_SET5               0xec
> +#define R63455_DISP_SET6               0xef
> +#define R63455_TE_GPIO_CTL             0xbe
> +#define R63455_PPS_SET                 0xe6

This is more details than we usually get, which is nice.

> +       r63455_dsi_write_seq(ctx, dsi_ctx, R63455_MF_CMD_ACCESS_PROTECT, 0x00);
> +       r63455_dsi_write_seq(ctx, dsi_ctx, R63455_SEQ_CTL, 0x00);
> +       r63455_dsi_write_seq(ctx, dsi_ctx,
> +                            R63455_DSI_CTL,
> +                            0x20, 0x6b, 0x80, 0x06, 0x33, 0x9a, 0x00, 0x1a,
> +                            0x7a);
> +       r63455_dsi_write_seq(ctx, dsi_ctx, R63455_DISP_MODE,
> +                            0x54, 0x00, 0x00, 0x00);
> +       r63455_dsi_write_seq(ctx, dsi_ctx, R63455_GEN_OUTPIN_SET,
> +                            0xf, 0xe4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +                            0xf, 0xb2, 0x00, 0x64);
> +       r63455_dsi_write_seq(ctx, dsi_ctx, R63455_DISP_SET3,
> +                            0x08, 0x70, 0x28, 0x48, 0x00, 0x00, 0x13, 0x21,
> +                            0xff, 0x00, 0x0f, 0x01, 0x14, 0x17, 0x00, 0x00,
> +                            0x00, 0x02, 0x40, 0x0C, 0x00, 0x00, 0x00, 0x20,
> +                            0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x70, 0x08,
> +                            0xD0, 0x02, 0x21, 0x6F, 0x08, 0x5A, 0x00, 0x00,
> +                            0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +                            0x00, 0x00, 0x00, 0x00, 0x00);
> +       r63455_dsi_write_seq(ctx, dsi_ctx, R63455_DISP_SET1,
> +                            RTN, 0x86, LE16_BYTE0(VBP), LE16_BYTE1(VBP), 0x08,
> +                            0x70, BE16_BYTE0(VFP), BE16_BYTE1(VFP), 0x00,
> +                            0x00, 0x08, 0x3B, 0x00, 0x00, 0x19, 0x01, 0x22);
> +       r63455_dsi_write_seq(ctx, dsi_ctx, R63455_DISP_SET3_2, 0x00);
> +       r63455_dsi_write_seq(ctx, dsi_ctx, R63455_DISP_SET4,
> +                            0x8b, 0x00, 0x80, 0x46, 0x61, 0x00, 0x8b);
> +       r63455_dsi_write_seq(ctx, dsi_ctx, R63455_DISP_SET5,
> +                            BE16_BYTE0(VID_VS_DELAY),
> +                            BE16_BYTE1(VID_VS_DELAY),
> +                            0x00, 0x00, 0x00);
> +       r63455_dsi_write_seq(ctx, dsi_ctx, R63455_DISP_SET6,
> +                            0x00, 0x24, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x00,
> +                            0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +                            0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +                            0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +                            0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +                            0x00, 0x00, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x03,
> +                            0x1D, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
> +                            0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
> +                            0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +                            0x00);
> +       r63455_dsi_write_seq(ctx, dsi_ctx, R63455_TE_GPIO_CTL,
> +                            0x00, 0x6A, 0x02);

So for the commands above we have a little more knowledge than just
opaque numbers about what the display controller is doing.

If you have a datasheet for this display controller, then please add some
one-line comments before each command to explain what is being set
up.

It still bugs me that we accept this much magic numbers in panel
drivers but I guess I just take a deep breath and live with it.

Yours,
Linus Walleij