Re: [RFC PATCH v2 1/3] arm64: add CPU prefetch and cache modulation sysfs interface

[Will Deacon]

On Wed, Aug 26, 2026 at 02:16:59AM +0800, Koba Ko wrote:
> Performance characterization on arm64 systems sometimes needs a way to
> inspect and bracket selected implementation-defined prefetch and cache
> controls without exposing raw register contents. Add an RFC-only arm64
> cpumod interface that presents a small set of named, range-checked
> per-CPU sysfs attributes under each CPU device.
> 
> Establish the Kconfig and Makefile plumbing, CPU profile detection for
> Grace and Vera from the target CPU's MIDR, register-field descriptors,
> per-CPU kobject and attribute helpers, locking, and target-CPU read/write
> callbacks. Common attributes are exposed for all supported profiles,
> while Grace- and Vera-specific fields are exposed only for the matching
> profile. Place the option at the end of the top-level Kernel Features
> menu because these implementation controls are not tied to an Arm
> architecture revision.
> 
> Per-CPU cpumod sysfs state follows the CPU lifecycle. Module
> initialization populates subtrees for every online CPU while holding
> cpus_read_lock(), so initial enumeration and CPU hotplug state
> registration are serialized against concurrent topology changes. Offline
> CPUs are intentionally skipped during initial setup because target-CPU
> MIDR detection requires an IPI-capable online CPU; a later online callback
> creates their subtree.
> 
> Profile detection reads MIDR through a synchronous callback on the CPU
> owning the sysfs subtree and returns nonzero only when that dispatch
> fails, so no IPI error can be hidden. After a successful read, retain
> CPUMOD_PROFILE_UNKNOWN as the unsupported-profile sentinel. Subtree
> creation skips that profile during both initial online enumeration and
> later CPUHP online callbacks without blocking module load or CPU hotplug.
> Object and sysfs setup failures remain fatal and are propagated.
> 
> Keep the dynamically allocated kobject state in a private per-CPU pointer
> instead of the CPU device's generic driver-data slot. The online callback
> is idempotent when that pointer already records a subtree. The offline
> callback clears the private pointer before dropping the kobject reference,
> allowing the release callback to retain ownership of the final free.
> 
> Register-backed controls are root-only read/write files. Reads
> synchronously execute on the target CPU and return the live register field
> value from that callback. Writes remain range-checked and continue to log
> the target-CPU readback after the register update.
> 
> Register the dynamic CPUHP state with
> cpuhp_setup_state_nocalls_cpuslocked(). The nocalls form avoids replaying
> startup callbacks for CPUs already initialized by the explicit online
> enumeration. On init failure, release the CPU read lock, destroy all
> subtrees created so far, and return the error. Module exit removes the
> CPUHP state with the matching nocalls helper and tears down all remaining
> per-CPU state across possible CPUs.
> 
> Reviewed-by: Fenghua Yu <fenghuay@xxxxxxxxxx>
> Reviewed-by: Tushar Dave <tdave@xxxxxxxxxx>
> Reviewed-by: Kai-Heng Feng <kaihengf@xxxxxxxxxx>
> Signed-off-by: Koba Ko <kobak@xxxxxxxxxx>
> ---
>  arch/arm64/Kconfig                      |  17 +
>  arch/arm64/kernel/Makefile              |   1 +
>  arch/arm64/kernel/arm_cpumod.c          | 458 ++++++++++++++++++++++++
>  arch/arm64/kernel/arm_cpumod_internal.h |  93 +++++
>  4 files changed, 569 insertions(+)
>  create mode 100644 arch/arm64/kernel/arm_cpumod.c
>  create mode 100644 arch/arm64/kernel/arm_cpumod_internal.h
> 
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index b3afe0688919b..5e4ada4884b89 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -2417,6 +2417,23 @@ config ARM64_CONTPTE
>  	  bit, for any mappings that meet the size and alignment requirements.
>  	  This reduces TLB pressure and improves performance.
>  
> +config ARM64_CPUMOD
> +	tristate "Arm CPU prefetch modulation sysfs controls"
> +	help
> +	  Expose selected CPU implementation control register fields through
> +	  per-CPU sysfs attributes for performance characterization.
> +
> +	  The exposed controls allow hardware prefetch and cache-management
> +	  policy fields to be inspected and adjusted on CPUs where firmware
> +	  permits EL1 access to the relevant implementation control registers.
> +	  Systems where firmware traps or blocks these writes cannot use this
> +	  interface.
> +
> +	  This interface is intended for controlled performance evaluation and
> +	  should not be enabled by default on production systems.
> +
> +	  If unsure, say N.

We don't tend to support these sort of implementation-defined features
as:

   - They're generally not something we can virtualise
   - The registers should not be accessible to the kernel in production
   - It's not clear what other bits are exposed in the registers
   - These sort of controls can't always be toggled while the memory system
     is active
   - We can't test them or maintain the zoo of interfaces we'd end up with
     if we started merging them

So exposing the registers directly to userspace doesn't feel like a
particularly good idea to me.

Will