[PATCH v5 8/9] clk: nuvoton: ma35d1: get HXT/LXT from DT

[Miquel Raynal]

HXT and LXT are crystal oscillator inputs of the clock controller, they
are described in the DT. Get them with devm_clk_get_optional() and point
the internal clock table at the clk_hw's found this way, instead of
registering fixed rate clocks in their place.

Old DTs reference the HXT fixed-clock without naming it and do not
describe LXT at all. In this case, fall back to the fixed rate clocks
that were used so far, to keep booting.

Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock controller")
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx>
---
 drivers/clk/nuvoton/clk-ma35d1.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c
index ceebcbd8c18b..81a412b1706e 100644
--- a/drivers/clk/nuvoton/clk-ma35d1.c
+++ b/drivers/clk/nuvoton/clk-ma35d1.c
@@ -4,6 +4,7 @@
  * Author: Chi-Fang Li <cfli0@xxxxxxxxxxx>
  */
 
+#include <linux/clk.h>
 #include <linux/clk-provider.h>
 #include <linux/mfd/syscon.h>
 #include <linux/module.h>
@@ -124,6 +125,21 @@ static struct clk_hw *ma35d1_clk_fixed(const char *name, int rate)
 	return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
 }
 
+static struct clk_hw *ma35d1_clk_xtal(struct device *dev, const char *name,
+				      unsigned long rate)
+{
+	struct clk *clk = devm_clk_get_optional(dev, name);
+
+	if (IS_ERR(clk))
+		return ERR_CAST(clk);
+
+	if (!clk)
+		/* Old DTs do not describe the crystal inputs. */
+		return ma35d1_clk_fixed(name, rate);
+
+	return __clk_get_hw(clk);
+}
+
 static struct clk_hw *ma35d1_clk_mux(struct device *dev, const char *name,
 				     void __iomem *reg, u8 shift, u8 width,
 				     struct clk_hw **hws,
@@ -240,10 +256,10 @@ static int ma35d1_clocks_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
-	hws[HXT] = ma35d1_clk_fixed("hxt", 24000000);
+	hws[HXT] = ma35d1_clk_xtal(dev, "hxt", 24000000);
 	hws[HXT_GATE] = ma35d1_clk_gate(dev, "hxt_gate", "hxt",
 					clk_base + REG_CLK_PWRCTL, 0);
-	hws[LXT] = ma35d1_clk_fixed("lxt", 32768);
+	hws[LXT] = ma35d1_clk_xtal(dev, "lxt", 32768);
 	hws[LXT_GATE] = ma35d1_clk_gate(dev, "lxt_gate", "lxt",
 					clk_base + REG_CLK_PWRCTL, 1);
 	hws[HIRC] = ma35d1_clk_fixed("hirc", 12000000);

-- 
2.55.0