[PATCH 6/6] arm64: dts: qcom: hawi: Add QPaCE DT node
From: Georgi Djakov
Date: Wed Sep 30 2026 - 14:18:56 EST
Add the device-tree node for the Qualcomm Page Compression Engine on
the Hawi platform.
Signed-off-by: Georgi Djakov <georgi.djakov@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/hawi.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hawi.dtsi b/arch/arm64/boot/dts/qcom/hawi.dtsi
index 6b0a0ff0faa4..283a5acfa073 100644
--- a/arch/arm64/boot/dts/qcom/hawi.dtsi
+++ b/arch/arm64/boot/dts/qcom/hawi.dtsi
@@ -5677,6 +5677,23 @@ llclpi_noc: interconnect@31310000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ qpace: compression@31400000 {
+ compatible = "qcom,hawi-qpace";
+ reg = <0x0 0x31400000 0x0 0x80000>;
+ iommus = <&apps_smmu 0x1c20 0x13>,
+ <&apps_smmu 0x1c24 0x13>,
+ <&apps_smmu 0x1c28 0x13>,
+ <&apps_smmu 0x1c2c 0x13>;
+ dma-coherent;
+ interconnects = <&gem_noc MASTER_QPACE QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qpace-mem";
+ interrupts = <GIC_ESPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ring-and-bus-err",
+ "urgent";
+ };
+
system-cache-controller@31800000 {
compatible = "qcom,hawi-llcc";
reg = <0x0 0x31800000 0x0 0x200000>,