RE: [PATCH v5 0/9] Add support for DU, LVDS and DSI on the Renesas RZ/G3L SoC
From: Biju Das
Date: Thu Oct 01 2026 - 06:59:52 EST
Hi All,
> -----Original Message-----
> From: Biju <biju.das.au@xxxxxxxxx>
> Sent: 01 October 2026 10:40
> Subject: [PATCH v5 0/9] Add support for DU, LVDS and DSI on the Renesas RZ/G3L SoC
>
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Hi All,
>
> This patch series aims to add DSI, LVDS and LCD support for the RZ/G3L SMARC EVK. The RZ/G3L LCDC is
> similar to the one found on RZ/G2L, but has LVDS support.
>
> The LVDS series [1] is merged here to get an overall picture.
>
> [1] https://lore.kernel.org/all/20260625172359.292631-1-biju.das.jz@xxxxxxxxxxxxxx/
>
> v4->v5:
> * Collected tag.
> * Restored mode_clock_min to 5440 kHz.
> * Replaced static resets array in probe with global resets array.
> * Updated rzg3l_lvds_atomic_disable() to fix the
> PM_RUNTIME_ACQUIRE_IF_ENABLED guard that prevents synchronous suspend.
> * Updated rzg3l_lvds_atomic_enable() to fix refcount underflow in
> atomic_disable due to early return in atomic_enable.
> * Dropped dotclk from struct rzg3l_lvds.
> v3->v4:
> * Collected tag.
> * Dropped pwrrdy variable from struct rzg2l_mipi_dsi_hw_info and instead
> using feature flag RZ_MIPI_DSI_FEATURE_PWRRDY
> * Dropped rzg2l_mipi_dsi_pwrrdy_off() as it is taken care by
> devm_pwrseq_get().
> * Updated mode_clock_min from 5440->5400 kHz.
> * Added resets in pair for simplification.
> * Added comment in probe() for asserting resets.
> * Updated commit description for patch#8 and #9.
> * Updated license header for patch#8 and #9.
> * Added HDMI audio support.
> * Dropped reg_1v8 and reg_3v3 nodes as they are redundant.
> * Renamed it6263 node name from it6263 to hdmi.
> v2->v3:
> * Dropped binding patches as it is accepted.
> v1->v2:
> * Dropped renesas,sysc-pwrrdy property as it is modelled as power
> sequence.
> * Switched to power sequence for handling pwrrdy signal.
> * Dropped header file regmap.h and mfd/syscon.h
> * Added header file pwrseq/consumer.h
> * Replaced syscon_field->pwrrdy in struct rzg3l_mipi_dsi_info.
> * Restored ports in DU bindings.
> * Replaced endpoint with port in ports node.
> * Dropped the macro RZG2L_DU_FEATURE_SMUX2_DSI_CLK and RZG2L_DU_MAX_LVDS.
> * Dropped the variable rcdu from struct rzg2l_du_encoder.
> * Dropped the variable lvds from struct rzg2l_du_device.
> * Dropped renesas,sysc-pwrrdy from dsi node.
>
> Biju Das (9):
> drm: renesas: rzg2l_mipi_dsi: Add dphyctrl0_init_val to hw_info
> drm: renesas: rzg2l_mipi_dsi: Add activation_dly to hw_info
> drm: renesas: rzg2l_mipi_dsi: Move global timings into hardware info
> struct
> drm: renesas: rzg2l_mipi_dsi: Add support for DSI PWRRDY
> drm: renesas: rzg2l_mipi_dsi: Add RZ/G3L MIPI DSI support
> drm: renesas: rz-du: Add RZ/G3L (R9A08G046) DU support
> drm: renesas: rz-du: Add support for RZ/G3L LVDS encoder
> arm64: dts: renesas: Add DSI overlay for RZ/G3L SMARC EVK with ADV7535
> arm64: dts: renesas: Add LVDS overlay for RZ/G3L SMARC EVK with
> ITE6263
>
> arch/arm64/boot/dts/renesas/Makefile | 6 +
> .../r9a08g046l48-smarc-dsi-adv7535.dtso | 138 +++++++++
> .../r9a08g046l48-smarc-lvds-ite6263.dtso | 86 ++++++
> drivers/gpu/drm/renesas/rz-du/Kconfig | 13 +
> drivers/gpu/drm/renesas/rz-du/Makefile | 1 +
> drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 24 +-
> drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 3 +-
> .../gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 24 ++
> .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 162 ++++++++++-
> drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c | 275 ++++++++++++++++++
> .../gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h | 25 ++
> 11 files changed, 749 insertions(+), 8 deletions(-) create mode 100644
> arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-dsi-adv7535.dtso
> create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-lvds-ite6263.dtso
> create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c
> create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h
>
> --
> 2.43.0
Applied patches 1..7 on drm-misc-next.
Cheers,
Biju