Re: [PATCH v4 3/3] arm64: dts: qcom: qcs6490-rb3gen2: add endpoint buses

[Greg KH]

On Fri, Sep 18, 2026 at 10:26:58AM -0500, Alex Elder wrote:
> The TC9564 SoC incorporates a PCIe switch, which is connected via
> the second PCI segment (0001) on the RB3gen2 platform.  The third
> downstream port of that switch (pcie@3,0) has an embedded PCIe
> endpoint that implements two PCIe functions.
> 
> The SoC implements other peripherals, and they will be accessed via
> PCI endpoint bus.  Define the devicetree nodes representing these
> buses, including the mapping of each BAR's address range to its
> local address space.
> 
> The endpoint's ranges property must be defined, but it will be
> updated dynamically to include all BARs.  As a result of this update,
> the parent address portion of each range will reflect the specific
> address assigned to the BAR.
> 
> Co-developed-by: Daniel Thompson <daniel@xxxxxxxxxxxx>
> Signed-off-by: Daniel Thompson <daniel@xxxxxxxxxxxx>
> Signed-off-by: Alex Elder <elder@xxxxxxxxxxxx>
> ---
>  arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 30 ++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> index 3bb5fca8e2b13..5b7f5292a8864 100644
> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> @@ -955,11 +955,41 @@ pcie@3,0 {
>  			bus-range = <0x5 0xff>;
>  
>  			dev@0,0 {
> +				compatible = "pci1179,0220";
>  				reg = <0x50000 0x0 0x0 0x0 0x0>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				/* Ranges will be updated dynamically */
> +				ranges = <0x0 0x0 0x0  0x83050000 0x0 0x0  0x0 0x4000>,
> +					 <0x2 0x0 0x0  0x83050000 0x0 0x4000  0x0 0x80000>,
> +					 <0x4 0x0 0x0  0x83050000 0x0 0x84000  0x0 0x200000>;
> +
> +				pci-ep-bus@4 {
> +					compatible = "simple-bus";
> +					#address-cells = <1>;
> +					#size-cells = <1>;
> +					/* Map 0x0-0x1fffff to BAR 4 */
> +					ranges = <0x0  0x4 0x0 0x0  0x200000>;
> +				};
>  			};
>  
>  			dev@0,1 {
> +				compatible = "pci1179,0220";
>  				reg = <0x50100 0x0 0x0 0x0 0x0>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				/* Ranges will be updated dynamically */
> +				ranges = <0x0 0x0 0x0  0x83050100 0x0 0x0  0x0 0x4000>,
> +					 <0x2 0x0 0x0  0x83050100 0x0 0x4000  0x0 0x80000>,
> +					 <0x4 0x0 0x0  0x83050100 0x0 0x84000  0x0 0x200000>;
> +
> +				pci-ep-bus@4 {
> +					compatible = "simple-bus";
> +					#address-cells = <1>;
> +					#size-cells = <1>;
> +					/* Map 0x0-0x1fffff to BAR 4 */
> +					ranges = <0x0  0x4 0x0 0x0  0x200000>;
> +				};
>  			};
>  		};
>  	};
> -- 
> 2.53.0
> 

This doesn't apply to the char-misc-testing branch :(

So I took the first two patches only.

thanks,

greg k-h