[PATCH 18/38] arm: dts: qcom: ipq4019: Align multiple property data
From: Waqar Hameed
Date: Thu Oct 01 2026 - 18:41:02 EST
Multiple property data on a newline should be aligned with the first
one. Found/fixed with dtfmt (Devicetree Source formatter).
Signed-off-by: Waqar Hameed <waqar.hameed@xxxxxxxx>
---
arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi | 10 +++++-----
arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts | 2 +-
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 8 ++++----
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi
index e998cb72c98db..faedcc0a76387 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi
@@ -32,7 +32,7 @@ serial_0_pins: serial0-state {
serial_1_pins: serial1-state {
pins = "gpio8", "gpio9",
- "gpio10", "gpio11";
+ "gpio10", "gpio11";
function = "blsp_uart1";
bias-disable;
};
@@ -60,10 +60,10 @@ i2c_0_pins: i2c-0-state {
nand_pins: nand-state {
pins = "gpio53", "gpio55", "gpio56",
- "gpio57", "gpio58", "gpio59",
- "gpio60", "gpio62", "gpio63",
- "gpio64", "gpio65", "gpio66",
- "gpio67", "gpio68", "gpio69";
+ "gpio57", "gpio58", "gpio59",
+ "gpio60", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68", "gpio69";
function = "qpic";
};
};
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts
index 71c5ba00ff982..4230d71c48b16 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -21,7 +21,7 @@ spi@78b6000 {
pinctrl@1000000 {
serial_1_pins: serial1-state {
pins = "gpio8", "gpio9",
- "gpio10", "gpio11";
+ "gpio10", "gpio11";
function = "blsp_uart1";
bias-disable;
};
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
index 6ff87808e2a0f..1fa1aef140a12 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
@@ -181,7 +181,7 @@ intc: interrupt-controller@b000000 {
#address-cells = <0>;
#interrupt-cells = <3>;
reg = <0x0b000000 0x1000>,
- <0x0b002000 0x1000>;
+ <0x0b002000 0x1000>;
};
gcc: clock-controller@1800000 {
@@ -268,7 +268,7 @@ blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
reg = <0x78b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
- <&gcc GCC_BLSP1_AHB_CLK>;
+ <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
@@ -380,7 +380,7 @@ blsp1_uart1: serial@78af000 {
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
- <&gcc GCC_BLSP1_AHB_CLK>;
+ <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 0>, <&blsp_dma 1>;
dma-names = "tx", "rx";
@@ -392,7 +392,7 @@ blsp1_uart2: serial@78b0000 {
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
- <&gcc GCC_BLSP1_AHB_CLK>;
+ <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 2>, <&blsp_dma 3>;
dma-names = "tx", "rx";
--
2.43.0