Re: [PATCH 3/4] crypto: hisilicon/qm - check queue depth read from hardware

From: Herbert Xu

Date: Fri Oct 02 2026 - 03:56:53 EST


On Thu, Sep 24, 2026 at 07:38:11PM +0800, Weili Qian wrote:
> When hardware is abnormal, queue depth values read from registers may
> be invalid, causing array out of bounds or division by zero.
>
> Add a QM_XQC_MIN_DEPTH check in qm_get_xqc_depth() so all callers are
> covered. The check only applies to QM_HW_V3 and later, where depth is
> read from registers.
>
> Fixes: 129a9f340172 ("crypto: hisilicon/qm - get qp num and depth from hardware registers")
> Signed-off-by: Weili Qian <qianweili@xxxxxxxxxx>
> ---
> drivers/crypto/hisilicon/qm.c | 34 +++++++++++++++++++++++++++++-----
> 1 file changed, 29 insertions(+), 5 deletions(-)

Please check

https://sashiko.dev/#/patchset/20260924113812.1110302-1-qianweili%40huawei.com

Thanks,
--
Email: Herbert Xu <herbert@xxxxxxxxxxxxxxxxxxx>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt