Re: [PATCH v8 02/15] media: ov8858: support 19.2 MHz clock and manual white balance

[Andy Shevchenko]

On Fri, Oct 2, 2026 at 11:17 AM <mauriziocasciano7@xxxxxxxxx> wrote:
>
> Support both 19.2 MHz and 24 MHz input clocks. Move the PLL and
> global-timing registers out of the common mode tables and select register
> settings for the detected revision, lane count, input clock and 360 MHz
> link frequency when starting the stream. Use the actual input-clock rate
> when calculating the reset delay.
>
> Add standard red and blue balance controls for the sensor's manual white
> balance registers. V4L2 defines red and blue balance relative to green but
> does not define a standard green-balance control, so keep green at unity.
> Accumulate errors while programming all three channels.
>
> The manual white-balance register definitions and programming follow
> Intel's GPL-2.0 OV5670 driver, so retain its 2017 Intel copyright notice.

...

> -#define OV8858_LINK_FREQ               360000000U
> -#define OV8858_XVCLK_FREQ              24000000
> +#define OV8858_LINK_FREQ               (360 * HZ_PER_MHZ)
> +#define OV8858_XVCLK_FREQ_24MHZ                (24 * HZ_PER_MHZ)
> +#define OV8858_XVCLK_FREQ_19_2MHZ      (19200 * HZ_PER_KHZ)


Sakari, you see, still inconsistent. If we really want to use
multipliers for XVCLK, I would prefer to see the same one, so 24000 *
HZ_PER_KHZ.

...

> +/* Keep input-clock programming separate from the common sensor setup. */
> +static const struct regval ov8858_24mhz_360mhz_r1a_2lane[] = {
> +       {0x0302, 0x1e},
> +       {0x0303, 0x00},
> +       {0x0304, 0x03},
> +       {0x030e, 0x00},
> +       {0x030f, 0x09},
> +       {0x0312, 0x01},
> +       {0x031e, 0x0c},
> +       {0x4837, 0x16},

> +       {REG_NULL, 0x00},

Please, drop trailing commas in the terminator entries, like above.

> +};

-- 
With Best Regards,
Andy Shevchenko