[PATCH v3 0/2] EDAC/amd64: Fix UMC csrow decode and consolidate Family 1Ah setup

[Vishal Badole]

Two small amd64_edac fixes/cleanups for AMD Family 1Ah.

Patch 1 is the fix: mask the UMC chip select with 0x3, not 0x7. Only
four chip selects exist, so the old mask could decode an out-of-range
csrow and trip an EDAC warning.

Patch 2 sets zn_regs_v2 once at the Family 1Ah level instead of in each
model case, so future models cannot miss the v2 register layout.

Changes since v2:
 - Patch 1 (fix): Simplified the commit message and updated the code
   comment.

Changes since v1:
 - Patch 1 (fix): Added Fixes: and Cc: stable, and move the fix first.
 - Patch 2 (cleanup): Updated the commit message.

v2: https://lore.kernel.org/all/20260928180935.472319-1-Vishal.Badole@xxxxxxx/
v1: https://lore.kernel.org/all/20260925172639.97063-1-Vishal.Badole@xxxxxxx/

Vishal Badole (2):
  EDAC/amd64: Mask UMC chip select to the four implemented selects
  EDAC/amd64: Set zn_regs_v2 for all Family 1Ah models

 drivers/edac/amd64_edac.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

-- 
2.34.1