[PATCH 06/15] mtd: spi-nor: Fix WRSR with ODTR chips
From: Miquel Raynal
Date: Fri Oct 02 2026 - 08:23:48 EST
The ODTR interface requires an even number of bytes in each section of
the operation. spi_nor_spimem_setup_op() takes care of the opcode phase,
but we have to adapt the rest of the operation ourself.
Inspiration comes from the spi_nor_read_sr_ll() helper which faces a
similar case.
Fixes: 63489002d397 ("mtd: spi-nor: Refactor Read Status/Write Status support")
Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx>
---
drivers/mtd/spi-nor/core.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 2bbec3feda39..6e22342361c3 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -791,6 +791,17 @@ static int spi_nor_write_sr_ll(struct spi_nor *nor, u8 opcode, const u8 *sr,
if (nor->spimem) {
struct spi_mem_op op = SPI_NOR_WRSR_OP(opcode,
nor->bouncebuf, len);
+ if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
+ if (len != 1)
+ return -EOPNOTSUPP;
+
+ /*
+ * We don't want to write only one byte in DTR mode. So,
+ * duplicate the buffer and write 2.
+ */
+ op.data.nbytes = 2;
+ nor->bouncebuf[1] = nor->bouncebuf[0];
+ }
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
--
2.55.0