Re: [PATCH v2 2/2] watchdog: s3c2410_wdt: Add support for Exynos8855 SoC
From: Peter Griffin
Date: Fri Oct 02 2026 - 11:05:23 EST
On Sun, 27 Sept 2026 at 16:09, Alim Akhtar <alim.akhtar@xxxxxxxxxxx> wrote:
>
> Watchdog IP on this SoC is similar to Exynos850/ExynosAutov{9/920}.
> This does not have CNT_EN_WDT bit in PMU and offset of RST_STAT is
> different then the previously support SoC.
> Reuse the offset as much as from already supported SoC
>
> Signed-off-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
> ---
Small nit: If you send another version, the last sentence could be
updated slightly for clarity. Something like
"Reuse the offsets as much as possible from already supported SoCs"
Reviewed-by: Peter Griffin <peter.griffin@xxxxxxxxxx>
>
> *Changes in V2:
> - Fixed Sashiko review comments
> - [Low] watchdog: confusing reuse of CLUSTER0 macro for CLUSTER1
> - [Low] watchdog: space-based alignment for EXYNOS8855_RST_STAT_REG_OFFSET
>
> drivers/watchdog/s3c2410_wdt.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index 7053963fb0ac..007c05ed2c7b 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c
> @@ -58,6 +58,7 @@
> #define S3C2410_WATCHDOG_DEFAULT_TIME (15)
>
> #define EXYNOS5_RST_STAT_REG_OFFSET 0x0404
> +#define EXYNOS8855_RST_STAT_REG_OFFSET 0x10
> #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408
> #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c
> #define EXYNOS850_CLUSTER0_NONCPU_OUT 0x1220
> @@ -73,6 +74,7 @@
>
> #define EXYNOS850_CLUSTER0_WDTRESET_BIT 24
> #define EXYNOS850_CLUSTER1_WDTRESET_BIT 23
> +#define EXYNOS8855_CLUSTER1_WDTRESET_BIT 25
> #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25
> #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24
> #define EXYNOSAUTOV920_CLUSTER0_WDTRESET_BIT 0
> @@ -281,6 +283,26 @@ static const struct s3c2410_wdt_variant drv_data_exynos850_cl1 = {
> QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
> };
>
> +static const struct s3c2410_wdt_variant drv_data_exynos8855_cl0 = {
> + .mask_reset_reg = EXYNOS850_CLUSTER0_NONCPU_INT_EN,
> + .mask_bit = 2,
> + .mask_reset_inv = true,
> + .rst_stat_reg = EXYNOS8855_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = EXYNOS850_CLUSTER0_WDTRESET_BIT,
> + .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
> + QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_DBGACK_BIT,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_exynos8855_cl1 = {
> + .mask_reset_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_INT_EN,
> + .mask_bit = 2,
> + .mask_reset_inv = true,
> + .rst_stat_reg = EXYNOS8855_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = EXYNOS8855_CLUSTER1_WDTRESET_BIT,
> + .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
> + QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_DBGACK_BIT,
> +};
> +
> static const struct s3c2410_wdt_variant drv_data_exynos990_cl0 = {
> .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> .mask_bit = 2,
> @@ -400,6 +422,8 @@ static const struct of_device_id s3c2410_wdt_match[] = {
> .data = &drv_data_exynos7 },
> { .compatible = "samsung,exynos850-wdt",
> .data = &drv_data_exynos850_cl0 },
> + { .compatible = "samsung,exynos8855-wdt",
> + .data = &drv_data_exynos8855_cl0 },
> { .compatible = "samsung,exynos990-wdt",
> .data = &drv_data_exynos990_cl0 },
> { .compatible = "samsung,exynosautov9-wdt",
> @@ -723,6 +747,7 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
> if (variant == &drv_data_exynos850_cl0 ||
> variant == &drv_data_exynosautov9_cl0 ||
> + variant == &drv_data_exynos8855_cl0 ||
> variant == &drv_data_gs101_cl0 ||
> variant == &drv_data_exynosautov920_cl0 ||
> variant == &drv_data_exynos990_cl0) {
> @@ -740,6 +765,8 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> case 1:
> if (variant == &drv_data_exynos850_cl0)
> variant = &drv_data_exynos850_cl1;
> + else if (variant == &drv_data_exynos8855_cl0)
> + variant = &drv_data_exynos8855_cl1;
> else if (variant == &drv_data_exynosautov9_cl0)
> variant = &drv_data_exynosautov9_cl1;
> else if (variant == &drv_data_gs101_cl0)
> --
> 2.34.1
>