Re: [PATCH] clk: tegra: Fix Tegra114 MIPI calibration clock parent

From: Brian Masney

Date: Fri Oct 02 2026 - 11:41:20 EST


Hi Mikko,

On Wed, Sep 30, 2026 at 02:18:34PM +0900, Mikko Perttunen wrote:
> CLK_MIPI_CAL on Tegra114 is a plain clock gate with no source mux; the
> fixed parent is PLL_P_OUT3, which is specified to run at 72 MHz. The
> clock driver currently registers the gate with clk_m as its parent, so
> the clock framework never enables PLL_P_OUT3 when MIPI_CAL is enabled,
> and reports the wrong rate for it.
>
> Register the gate with pll_p_out3 as its parent. Also drop
> CLK_SET_RATE_PARENT at the same time: the parent canonically runs at
> 72 MHz so we shouldn't change the rate.
>
> Signed-off-by: Mikko Perttunen <mperttunen@xxxxxxxxxx>

Should there be a Fixes tag? I see that Thierry made a change to this
same clock 11 years ago:

commit 07314fc108e195044c074f4b443974b5aaa2d5d7
Author: Thierry Reding <treding@xxxxxxxxxx>
Date: Wed Apr 8 16:48:26 2015 +0200

clk: tegra: Special-case mipi-cal parent on Tegra114

Starting with Tegra124, the mipi-cal clock uses the 72 MHz clock as its
source. On Tegra114 this clock's parent was clk_m, so it is the one-off
chip.

Brian


> ---
> drivers/clk/tegra/clk-tegra114.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> index f1bca81b7776..97f5500b13b5 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -1050,8 +1050,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
> &emc_lock);
> clks[TEGRA114_CLK_MC] = clk;
>
> - clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
> - CLK_SET_RATE_PARENT, 56,
> + clk = tegra_clk_register_periph_gate("mipi-cal", "pll_p_out3", 0,
> + clk_base, 0, 56,
> periph_clk_enb_refcnt);
> clks[TEGRA114_CLK_MIPI_CAL] = clk;
>
>
> ---
> base-commit: 72d3fcf802c45d00b300f25b848a93c3a2bd7c7e
> change-id: 20260930-b4-dalmore-fixes-mipical-clk-eb375008dd66
>