[PATCH 56/74] media: qcom: camss: csid-gen3: Route IPP completions to the port the IPP feeds

[bod]

From: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>

The pixel and stats completion groups sit below the first RDI bit in
CSID_BUF_DONE_IRQ_STATUS. csid_isr() hands them to port 0, which only
holds for Valve's NV12-on-RDI, where the IPP output is written through
RDI0's line.

Record the source port csid_configure_stream() routed through the IPP
and complete the groups there. That is the PIX line when it is
streaming, and RDI0 on the NV12-on-RDI path as before.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>
---
 drivers/media/platform/qcom/camss/camss-csid.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h
index 400995f35f0ef..b67cb1306acf2 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.h
+++ b/drivers/media/platform/qcom/camss/camss-csid.h
@@ -161,6 +161,7 @@ struct csid_device {
 	u32 irq;
 	char irq_name[30];
 	u32 reg_update;
+	u8 ipp_port;	/* source port the IPP feeds: PIX, or RDI0 for NV12 compat */
 	struct camss_clock *clock;
 	int nclocks;
 	struct regulator_bulk_data *supplies;

-- 
2.55.0