Re: [PATCH 02/15] PCI: Add an offset-indexed store for saved capability registers

[Josh Hilke]

On Thu, Sep 24, 2026 at 10:34 AM David Matlack <dmatlack@xxxxxxxxxx> wrote:
>   - Each capability allocates its own buffer, at nine call sites (plus
>     one hand-built by a quirk) that can each fail independently. Four of
>     them (AER, DPC, PTM, TPH) ignore the failure

 After patch 1, DPC reports the failure with pci_err(), so at this
point only AER, PTM and TPH ignore it.

> +     *val = dword >> (8 * (off & (sizeof(u32) - 1)));

[...]

> +     unsigned int shift = 8 * (off & (sizeof(u32) - 1));

Nit: please put this shift in one small helper so the two copies can't
drift.

- Josh Hilke





- Josh Hilke