[PATCH 12/45] media: qcom: camss: sm8250: add IFE Lite top v10x

From: Gjorgji . Rosikopulos . gjorgji . rosikopulos

Date: Tue Oct 06 2026 - 18:47:46 EST

From: Atanas Filipov <atanas.filipov@xxxxxxxxxxxxxxxx>

Add the IFE top controller used by the SM8250 lite pixel path.

Signed-off-by: Atanas Filipov <atanas.filipov@xxxxxxxxxxxxxxxx>
---
drivers/media/platform/qcom/camss/Makefile | 1 +
.../qcom/camss/camss-ife-lite-top-v10x.c | 387 ++++++++++++++++++
drivers/media/platform/qcom/camss/camss-ife.h | 2 +
3 files changed, 390 insertions(+)
create mode 100644 drivers/media/platform/qcom/camss/camss-ife-lite-top-v10x.c

diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
index f26806c69e14..22df889656ba 100644
--- a/drivers/media/platform/qcom/camss/Makefile
+++ b/drivers/media/platform/qcom/camss/Makefile
@@ -16,6 +16,7 @@ qcom-camss-objs += \
camss-format.o \
camss-ife-bus-v20x.o \
camss-ife-camif-v10x.o \
+ camss-ife-lite-top-v10x.o \
camss-ife-mod-v10x.o \
camss-ife-scale-v10x.o \
camss-ife-top-v20x.o \
diff --git a/drivers/media/platform/qcom/camss/camss-ife-lite-top-v10x.c b/drivers/media/platform/qcom/camss/camss-ife-lite-top-v10x.c
new file mode 100644
index 000000000000..79b270b3a712
--- /dev/null
+++ b/drivers/media/platform/qcom/camss/camss-ife-lite-top-v10x.c
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (c) 2023, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Technologies, Inc.
+ */
+
+#include "camss-ife-camif-v10x.h"
+#include "camss-ife.h"
+#include "camss.h"
+
+#define IFE_LT_V10X_TOP_OFFS 0x0000
+#define IFE_LT_V10X_CAMIF_RDI_OFFSET (IFE_LT_V10X_TOP_OFFS + 0x1200)
+
+#define IFE_LT_V10X_MOD_VER_MAJOR GENMASK(31, 28)
+#define IFE_LT_V10X_MOD_VER_MINOR GENMASK(27, 16)
+#define IFE_LT_V10X_MOD_VER_STEPS GENMASK(15, 0)
+#define IFE_LT_V10X_MOD_MAJOR_VERSION(val) FIELD_GET(IFE_LT_V10X_MOD_VER_MAJOR, val)
+#define IFE_LT_V10X_MOD_MINOR_VERSION(val) FIELD_GET(IFE_LT_V10X_MOD_VER_MINOR, val)
+#define IFE_LT_V10X_MOD_STEPS_VERSION(val) FIELD_GET(IFE_LT_V10X_MOD_VER_STEPS, val)
+
+/* CSID-level reset and register-update (via csid_base) */
+#define IFE_LT_V10X_TOP_RST_CMD_CORE_SW_RST BIT(1)
+#define IFE_LT_V10X_IIF_IRQ_RUPD_GROUP0 BIT(0)
+#define IFE_LT_V10X_IIF_IRQ_RUPD_GROUP1 BIT(1)
+#define IFE_LT_V10X_IIF_IRQ_RUPD_GROUP2 BIT(2)
+#define IFE_LT_V10X_IIF_IRQ_RUPD_GROUP3 BIT(3)
+#define IFE_LT_V10X_TOP_IRQ_CMD_CLEAR BIT(0)
+#define IFE_LT_V10X_TOP_IRQ_S0_RST_DONE BIT(17)
+#define IFE_LT_V10X_TOP_IRQ_S0_RDI3_FRAME_DROP BIT(8)
+#define IFE_LT_V10X_TOP_IRQ_S0_RDI2_FRAME_DROP BIT(7)
+
+/* TOP functional IRQ registers */
+#define IFE_LT_V10X_TOP_IRQ_S0_RDI1_FRAME_DROP BIT(6)
+#define IFE_LT_V10X_TOP_IRQ_S0_RDI0_FRAME_DROP BIT(5)
+#define IFE_LT_V10X_TOP_IRQ_S0_BUSWR BIT(4)
+#define IFE_LT_V10X_TOP_IRQ_S0_RDI3_OVERFLOW BIT(3)
+#define IFE_LT_V10X_TOP_IRQ_S0_RDI2_OVERFLOW BIT(2)
+#define IFE_LT_V10X_TOP_IRQ_S0_RDI1_OVERFLOW BIT(1)
+#define IFE_LT_V10X_TOP_IRQ_S0_RDI0_OVERFLOW BIT(0)
+
+#define IFE_LT_V10X_TOP_IRQ_S0_ERRORS_MASK \
+ (IFE_LT_V10X_TOP_IRQ_S0_RDI3_FRAME_DROP | \
+ IFE_LT_V10X_TOP_IRQ_S0_RDI2_FRAME_DROP | \
+ IFE_LT_V10X_TOP_IRQ_S0_RDI1_FRAME_DROP | \
+ IFE_LT_V10X_TOP_IRQ_S0_RDI0_FRAME_DROP | \
+ IFE_LT_V10X_TOP_IRQ_S0_RDI3_OVERFLOW | \
+ IFE_LT_V10X_TOP_IRQ_S0_RDI2_OVERFLOW | \
+ IFE_LT_V10X_TOP_IRQ_S0_RDI1_OVERFLOW | \
+ IFE_LT_V10X_TOP_IRQ_S0_RDI0_OVERFLOW)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI3_CAMIF_EPOCH1 BIT(15)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI3_CAMIF_EPOCH0 BIT(14)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI3_CAMIF_EOF BIT(13)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI3_CAMIF_SOF BIT(12)
+
+/* IRQ_STATUS_1 bits - per-RDI SOF/EOF/EPOCH */
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI2_CAMIF_EPOCH1 BIT(11)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI2_CAMIF_EPOCH0 BIT(10)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI2_CAMIF_EOF BIT(9)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI2_CAMIF_SOF BIT(8)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI1_CAMIF_EPOCH1 BIT(7)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI1_CAMIF_EPOCH0 BIT(6)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI1_CAMIF_EOF BIT(5)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI1_CAMIF_SOF BIT(4)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI0_CAMIF_EPOCH1 BIT(3)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI0_CAMIF_EPOCH0 BIT(2)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI0_CAMIF_EOF BIT(1)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI0_CAMIF_SOF BIT(0)
+
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI0 \
+ (IFE_LT_V10X_TOP_IRQ_S1_RDI0_CAMIF_EPOCH1 | \
+ IFE_LT_V10X_TOP_IRQ_S1_RDI0_CAMIF_EPOCH0 | \
+ IFE_LT_V10X_TOP_IRQ_S1_RDI0_CAMIF_EOF | \
+ IFE_LT_V10X_TOP_IRQ_S1_RDI0_CAMIF_SOF)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI1 \
+ (IFE_LT_V10X_TOP_IRQ_S1_RDI1_CAMIF_EPOCH1 | \
+ IFE_LT_V10X_TOP_IRQ_S1_RDI1_CAMIF_EPOCH0 | \
+ IFE_LT_V10X_TOP_IRQ_S1_RDI1_CAMIF_EOF | \
+ IFE_LT_V10X_TOP_IRQ_S1_RDI1_CAMIF_SOF)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI2 \
+ (IFE_LT_V10X_TOP_IRQ_S1_RDI2_CAMIF_EPOCH1 | \
+ IFE_LT_V10X_TOP_IRQ_S1_RDI2_CAMIF_EPOCH0 | \
+ IFE_LT_V10X_TOP_IRQ_S1_RDI2_CAMIF_EOF | \
+ IFE_LT_V10X_TOP_IRQ_S1_RDI2_CAMIF_SOF)
+#define IFE_LT_V10X_TOP_IRQ_S1_RDI3 \
+ (IFE_LT_V10X_TOP_IRQ_S1_RDI3_CAMIF_EPOCH1 | \
+ IFE_LT_V10X_TOP_IRQ_S1_RDI3_CAMIF_EPOCH0 | \
+ IFE_LT_V10X_TOP_IRQ_S1_RDI3_CAMIF_EOF | \
+ IFE_LT_V10X_TOP_IRQ_S1_RDI3_CAMIF_SOF)
+
+#define IFE_LT_V10X_TOP_IRQ_S2_DIAG_VIOLATION_IRQ BIT(12)
+#define IFE_LT_V10X_TOP_IRQ_S2_RDI3_CAMIF_VIOLATION BIT(11)
+#define IFE_LT_V10X_TOP_IRQ_S2_RDI2_CAMIF_VIOLATION BIT(10)
+#define IFE_LT_V10X_TOP_IRQ_S2_RDI1_CAMIF_VIOLATION BIT(9)
+#define IFE_LT_V10X_TOP_IRQ_S2_RDI0_CAMIF_VIOLATION BIT(8)
+
+#define IFE_LT_V10X_TOP_IRQ_S2_ERRORS_MASK \
+ (IFE_LT_V10X_TOP_IRQ_S2_DIAG_VIOLATION_IRQ | \
+ IFE_LT_V10X_TOP_IRQ_S2_RDI3_CAMIF_VIOLATION | \
+ IFE_LT_V10X_TOP_IRQ_S2_RDI2_CAMIF_VIOLATION | \
+ IFE_LT_V10X_TOP_IRQ_S2_RDI1_CAMIF_VIOLATION | \
+ IFE_LT_V10X_TOP_IRQ_S2_RDI0_CAMIF_VIOLATION)
+
+#define IFE_LT_V10X_HW_VERSION 0x00000000
+#define IFE_LT_V10X_RST_CMD 0x0000000c
+#define IFE_LT_V10X_REG_UPDATE_CMD 0x00000020
+#define IFE_LT_V10X_IRQ_CMD 0x00000024
+#define IFE_LT_V10X_IRQ_MASK_S0 0x00000028
+#define IFE_LT_V10X_IRQ_MASK_S1 0x0000002c
+#define IFE_LT_V10X_IRQ_MASK_S2 0x00000030
+#define IFE_LT_V10X_IRQ_CLEAR_S0 0x00000034
+#define IFE_LT_V10X_IRQ_CLEAR_S1 0x00000038
+#define IFE_LT_V10X_IRQ_CLEAR_S2 0x0000003c
+#define IFE_LT_V10X_IRQ_STATUS_S0 0x00000040
+#define IFE_LT_V10X_IRQ_STATUS_S1 0x00000044
+#define IFE_LT_V10X_IRQ_STATUS_S2 0x00000048
+
+static int ife_lite_top_10x_acquire(struct ife_device *ife, void __iomem *base,
+ void __iomem *csid_base)
+{
+ struct ife_top_ctx *ctx = &ife->top_ctx;
+
+ ctx->base = base + IFE_LT_V10X_TOP_OFFS;
+ ctx->rdi_base = base + IFE_LT_V10X_CAMIF_RDI_OFFSET;
+ ctx->camif_ops = ife->res->camif_ops;
+ ctx->dev = ife->camss->dev;
+
+ return 0;
+}
+
+static void ife_lite_top_10x_release(struct ife_top_ctx *ctx)
+{
+ ctx->base = NULL;
+ ctx->camif_ops = NULL;
+}
+
+static int ife_lite_top_10x_pipe_config(struct ife_top_ctx *ctx,
+ const struct ife_pad_desc *desc,
+ const struct camss_ife_pipeline_cfg *pipeline_cfg,
+ const struct camss_ife_wm_config *wm_cfg)
+{
+ const struct ife_hw_camif_ops *camif_ops = ctx->camif_ops;
+ enum camss_ife_hw_pipe hw_pipe = desc->hw_pipe;
+
+ switch (hw_pipe) {
+ case CAMSS_IFE_HW_PIPE_RDI0:
+ case CAMSS_IFE_HW_PIPE_RDI1:
+ case CAMSS_IFE_HW_PIPE_RDI2:
+ case CAMSS_IFE_HW_PIPE_RDI3:
+ camif_ops->config(ctx->rdi_base +
+ IFE_CAMIF_V10X_RDIX_OFFS(hw_pipe), hw_pipe, pipeline_cfg);
+ break;
+ default:
+ dev_err(ctx->dev, "Invalid pipeline identifier: 0x%x\n", hw_pipe);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ife_lite_top_10x_pipe_enable(struct ife_top_ctx *ctx,
+ const struct ife_pad_desc *desc)
+{
+ const struct ife_hw_camif_ops *camif_ops = ctx->camif_ops;
+ enum camss_ife_hw_pipe hw_pipe = desc->hw_pipe;
+
+ switch (hw_pipe) {
+ case CAMSS_IFE_HW_PIPE_RDI0:
+ case CAMSS_IFE_HW_PIPE_RDI1:
+ case CAMSS_IFE_HW_PIPE_RDI2:
+ case CAMSS_IFE_HW_PIPE_RDI3:
+ camif_ops->enable(ctx->rdi_base + IFE_CAMIF_V10X_RDIX_OFFS(hw_pipe),
+ hw_pipe);
+ break;
+ default:
+ dev_err(ctx->dev, "Invalid pipeline identifier: 0x%x\n", hw_pipe);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ife_lite_top_10x_pipe_disable(struct ife_top_ctx *ctx,
+ const struct ife_pad_desc *desc)
+{
+ const struct ife_hw_camif_ops *camif_ops = ctx->camif_ops;
+ enum camss_ife_hw_pipe hw_pipe = desc->hw_pipe;
+
+ switch (hw_pipe) {
+ case CAMSS_IFE_HW_PIPE_RDI0:
+ case CAMSS_IFE_HW_PIPE_RDI1:
+ case CAMSS_IFE_HW_PIPE_RDI2:
+ case CAMSS_IFE_HW_PIPE_RDI3:
+ camif_ops->disable(ctx->rdi_base + IFE_CAMIF_V10X_RDIX_OFFS(hw_pipe),
+ hw_pipe);
+ break;
+ default:
+ dev_err(ctx->dev, "Invalid pipeline identifier: 0x%x\n", hw_pipe);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static u32 ife_lite_top_10x_version(struct ife_top_ctx *ctx)
+{
+ void __iomem *base = ctx->base;
+ u32 reg = readl_relaxed(base + IFE_LT_V10X_HW_VERSION);
+ struct camss_hw_version hw_ver;
+
+ hw_ver.ids.major = IFE_LT_V10X_MOD_MAJOR_VERSION(reg);
+ hw_ver.ids.minor = IFE_LT_V10X_MOD_MINOR_VERSION(reg);
+ hw_ver.ids.steps = IFE_LT_V10X_MOD_STEPS_VERSION(reg);
+
+ return hw_ver.hw_version;
+}
+
+static void ife_lite_top_10x_reset(struct ife_top_ctx *ctx)
+{
+ void __iomem *base = ctx->base;
+
+ writel_relaxed(~0, base + IFE_LT_V10X_IRQ_CLEAR_S0);
+ writel_relaxed(~0, base + IFE_LT_V10X_IRQ_CLEAR_S1);
+ writel_relaxed(~0, base + IFE_LT_V10X_IRQ_CLEAR_S2);
+ writel_relaxed(IFE_LT_V10X_TOP_IRQ_S0_RST_DONE,
+ base + IFE_LT_V10X_IRQ_MASK_S0);
+ writel_relaxed(IFE_LT_V10X_TOP_RST_CMD_CORE_SW_RST, base + IFE_LT_V10X_RST_CMD);
+}
+
+static void ife_lite_top_10x_reg_update(struct ife_top_ctx *ctx,
+ const struct ife_pad_desc *dsc)
+{
+ void __iomem *base = ctx->base;
+
+ switch (dsc->hw_pipe) {
+ case CAMSS_IFE_HW_PIPE_RDI0:
+ writel_relaxed(IFE_LT_V10X_IIF_IRQ_RUPD_GROUP0, base + IFE_LT_V10X_REG_UPDATE_CMD);
+ break;
+ case CAMSS_IFE_HW_PIPE_RDI1:
+ writel_relaxed(IFE_LT_V10X_IIF_IRQ_RUPD_GROUP1, base + IFE_LT_V10X_REG_UPDATE_CMD);
+ break;
+ case CAMSS_IFE_HW_PIPE_RDI2:
+ writel_relaxed(IFE_LT_V10X_IIF_IRQ_RUPD_GROUP2, base + IFE_LT_V10X_REG_UPDATE_CMD);
+ break;
+ case CAMSS_IFE_HW_PIPE_RDI3:
+ writel_relaxed(IFE_LT_V10X_IIF_IRQ_RUPD_GROUP3, base + IFE_LT_V10X_REG_UPDATE_CMD);
+ break;
+ default:
+ dev_warn(ctx->dev, "The requested RUP is invalid: 0x%x\n", dsc->hw_pipe);
+ }
+}
+
+static void ife_lite_top_10x_prepare(struct ife_top_ctx *ctx)
+{
+ void __iomem *base = ctx->base;
+ u32 rval;
+
+ /* Clear pending interrupts */
+ writel_relaxed(~0, base + IFE_LT_V10X_IRQ_CLEAR_S0);
+ writel_relaxed(~0, base + IFE_LT_V10X_IRQ_CLEAR_S1);
+ writel_relaxed(~0, base + IFE_LT_V10X_IRQ_CLEAR_S2);
+ writel_relaxed(IFE_LT_V10X_TOP_IRQ_CMD_CLEAR, base + IFE_LT_V10X_IRQ_CMD);
+
+ /* Enable common, frame drops and overflow interrupts */
+ rval = IFE_LT_V10X_TOP_IRQ_S0_BUSWR | IFE_LT_V10X_TOP_IRQ_S0_ERRORS_MASK;
+ writel_relaxed(rval, base + IFE_LT_V10X_IRQ_MASK_S0);
+
+ /* Enable violation error interrupts */
+ rval = IFE_LT_V10X_TOP_IRQ_S2_ERRORS_MASK;
+ writel_relaxed(rval, base + IFE_LT_V10X_IRQ_MASK_S2);
+}
+
+static void ife_lite_top_10x_enable(struct ife_top_ctx *ctx, enum camss_ife_hw_pipe hw_pipe)
+{
+ void __iomem *base = ctx->base;
+ u32 mask;
+ u32 rval;
+
+ switch (hw_pipe) {
+ case CAMSS_IFE_HW_PIPE_RDI0:
+ mask = IFE_LT_V10X_TOP_IRQ_S1_RDI0;
+ break;
+ case CAMSS_IFE_HW_PIPE_RDI1:
+ mask = IFE_LT_V10X_TOP_IRQ_S1_RDI1;
+ break;
+ case CAMSS_IFE_HW_PIPE_RDI2:
+ mask = IFE_LT_V10X_TOP_IRQ_S1_RDI2;
+ break;
+ case CAMSS_IFE_HW_PIPE_RDI3:
+ mask = IFE_LT_V10X_TOP_IRQ_S1_RDI3;
+ break;
+ default:
+ WARN_ONCE(true, "The hw_pipe is invalid: 0x%x\n", hw_pipe);
+ return;
+ }
+
+ rval = readl_relaxed(base + IFE_LT_V10X_IRQ_MASK_S1);
+ writel_relaxed(rval | mask, base + IFE_LT_V10X_IRQ_MASK_S1);
+}
+
+static void ife_lite_top_10x_disable(struct ife_top_ctx *ctx, enum camss_ife_hw_pipe hw_pipe)
+{
+ void __iomem *base = ctx->base;
+ u32 mask;
+ u32 rval;
+
+ switch (hw_pipe) {
+ case CAMSS_IFE_HW_PIPE_RDI0:
+ mask = IFE_LT_V10X_TOP_IRQ_S1_RDI0;
+ break;
+ case CAMSS_IFE_HW_PIPE_RDI1:
+ mask = IFE_LT_V10X_TOP_IRQ_S1_RDI1;
+ break;
+ case CAMSS_IFE_HW_PIPE_RDI2:
+ mask = IFE_LT_V10X_TOP_IRQ_S1_RDI2;
+ break;
+ case CAMSS_IFE_HW_PIPE_RDI3:
+ mask = IFE_LT_V10X_TOP_IRQ_S1_RDI3;
+ break;
+ default:
+ WARN_ONCE(true, "The hw_pipe is invalid: 0x%x\n", hw_pipe);
+ return;
+ }
+
+ rval = readl_relaxed(base + IFE_LT_V10X_IRQ_MASK_S1);
+ writel_relaxed(rval & ~mask, base + IFE_LT_V10X_IRQ_MASK_S1);
+}
+
+static void ife_lite_top_10x_irq_status(struct ife_top_ctx *ctx, u32 isr_stat[IFE_TOP_STATUS_MAX])
+{
+ void __iomem *base = ctx->base;
+ u32 top_stat;
+
+ top_stat = readl_relaxed(base + IFE_LT_V10X_IRQ_STATUS_S0);
+ writel_relaxed(top_stat, base + IFE_LT_V10X_IRQ_CLEAR_S0);
+
+ isr_stat[IFE_TOP_STATUS_ID0] = 0;
+
+ if (top_stat & IFE_LT_V10X_TOP_IRQ_S0_RST_DONE)
+ isr_stat[IFE_TOP_STATUS_ID0] = IFE_HW_TOP_IRQ0_RST_DONE;
+
+ if (top_stat & IFE_LT_V10X_TOP_IRQ_S0_BUSWR)
+ isr_stat[IFE_TOP_STATUS_ID0] |= IFE_HW_TOP_IRQ0_BUSWR;
+
+ if (top_stat & IFE_LT_V10X_TOP_IRQ_S0_ERRORS_MASK)
+ isr_stat[IFE_TOP_STATUS_ID0] |= top_stat & IFE_LT_V10X_TOP_IRQ_S0_ERRORS_MASK;
+
+ top_stat = readl_relaxed(base + IFE_LT_V10X_IRQ_STATUS_S1);
+ writel_relaxed(top_stat, base + IFE_LT_V10X_IRQ_CLEAR_S1);
+
+ isr_stat[IFE_TOP_STATUS_ID1] = 0;
+
+ if (top_stat & IFE_LT_V10X_TOP_IRQ_S1_RDI0_CAMIF_SOF)
+ isr_stat[IFE_TOP_STATUS_ID1] |= IFE_HW_TOP_IRQ1_RDI0_SOF;
+
+ if (top_stat & IFE_LT_V10X_TOP_IRQ_S1_RDI1_CAMIF_SOF)
+ isr_stat[IFE_TOP_STATUS_ID1] |= IFE_HW_TOP_IRQ1_RDI1_SOF;
+
+ if (top_stat & IFE_LT_V10X_TOP_IRQ_S1_RDI2_CAMIF_SOF)
+ isr_stat[IFE_TOP_STATUS_ID1] |= IFE_HW_TOP_IRQ1_RDI2_SOF;
+
+ if (top_stat & IFE_LT_V10X_TOP_IRQ_S1_RDI3_CAMIF_SOF)
+ isr_stat[IFE_TOP_STATUS_ID1] |= IFE_HW_TOP_IRQ1_RDI3_SOF;
+
+ top_stat = readl_relaxed(base + IFE_LT_V10X_IRQ_STATUS_S2);
+ writel_relaxed(top_stat, base + IFE_LT_V10X_IRQ_CLEAR_S2);
+
+ isr_stat[IFE_TOP_STATUS_ID2] = 0;
+
+ if (top_stat & IFE_LT_V10X_TOP_IRQ_S2_ERRORS_MASK)
+ isr_stat[IFE_TOP_STATUS_ID2] |= top_stat & IFE_LT_V10X_TOP_IRQ_S2_ERRORS_MASK;
+
+ writel_relaxed(IFE_LT_V10X_TOP_IRQ_CMD_CLEAR, base + IFE_LT_V10X_IRQ_CMD);
+}
+
+const struct ife_hw_top_ops ife_lite_top_10x_ops = {
+ .acquire = ife_lite_top_10x_acquire,
+ .release = ife_lite_top_10x_release,
+ .version = ife_lite_top_10x_version,
+ .prepare = ife_lite_top_10x_prepare,
+ .enable = ife_lite_top_10x_enable,
+ .disable = ife_lite_top_10x_disable,
+ .pipe_config = ife_lite_top_10x_pipe_config,
+ .pipe_enable = ife_lite_top_10x_pipe_enable,
+ .pipe_disable = ife_lite_top_10x_pipe_disable,
+ .reg_update = ife_lite_top_10x_reg_update,
+ .reset = ife_lite_top_10x_reset,
+ .irq_status = ife_lite_top_10x_irq_status,
+};
diff --git a/drivers/media/platform/qcom/camss/camss-ife.h b/drivers/media/platform/qcom/camss/camss-ife.h
index 258af76c94ea..a36efd8a6352 100644
--- a/drivers/media/platform/qcom/camss/camss-ife.h
+++ b/drivers/media/platform/qcom/camss/camss-ife.h
@@ -393,4 +393,6 @@ extern const struct ife_hw_top_ops ife_top_20x_ops;
extern const struct ife_hw_buswr_ops ife_buswr_20x_ops;
extern const struct camss_mod_ops ife_mod_v10x_ops;

+extern const struct ife_hw_top_ops ife_lite_top_10x_ops;
+
#endif /* CAMSS_IFE_SUB_DEV_H */
--
2.34.1