[PATCH RESEND 34/45] media: qcom: camss: sa8775p: add pixel path resources
From: Gjorgji . Rosikopulos . gjorgji . rosikopulos
Date: Wed Oct 07 2026 - 05:19:15 EST
From: Atanas Filipov <atanas.filipov@xxxxxxxxxxxxxxxx>
Describe the CSIPHY, CSID, IFE, and IFE Lite resources used by the
SA8775P pixel path. Add a separate compatible so the new path can be
enabled without changing the legacy resources.
Co-developed-by: Vikram Sharma <vikram.sharma@xxxxxxxxxxxxxxxx>
Signed-off-by: Vikram Sharma <vikram.sharma@xxxxxxxxxxxxxxxx>
Co-developed-by: Prashant Shrotriya <prashant.shrotriya@xxxxxxxxxxxxxxxx>
Signed-off-by: Prashant Shrotriya <prashant.shrotriya@xxxxxxxxxxxxxxxx>
Signed-off-by: Atanas Filipov <atanas.filipov@xxxxxxxxxxxxxxxx>
---
drivers/media/platform/qcom/camss/camss.c | 424 ++++++++++++++++++++++
1 file changed, 424 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 7a3e5e6f81e1..a0b51c12c0bf 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -4382,6 +4382,412 @@ static const struct camss_subdev_resources vfe_res_8775p[] = {
},
};
+static const struct camss_subdev_resources csiphy_res_sa8775p_pix[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = {
+ { .supply = "vdda-phy", .init_load_uA = 15900 },
+ { .supply = "vdda-pll", .init_load_uA = 8900 }
+ },
+ .clock = { "csiphy_rx", "csiphy0", "csiphy0_timer" },
+ .clock_rate = {
+ { 400000000 },
+ { 0 },
+ { 400000000 },
+ },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .id = 0,
+ .streams_enable = true,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY1 */
+ {
+ .regulators = {
+ { .supply = "vdda-phy", .init_load_uA = 15900 },
+ { .supply = "vdda-pll", .init_load_uA = 8900 }
+ },
+ .clock = { "csiphy_rx", "csiphy1", "csiphy1_timer" },
+ .clock_rate = {
+ { 400000000 },
+ { 0 },
+ { 400000000 },
+ },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .id = 1,
+ .streams_enable = true,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY2 */
+ {
+ .regulators = {
+ { .supply = "vdda-phy", .init_load_uA = 15900 },
+ { .supply = "vdda-pll", .init_load_uA = 8900 }
+ },
+ .clock = { "csiphy_rx", "csiphy2", "csiphy2_timer" },
+ .clock_rate = {
+ { 400000000 },
+ { 0 },
+ { 400000000 },
+ },
+ .reg = { "csiphy2" },
+ .interrupt = { "csiphy2" },
+ .csiphy = {
+ .id = 2,
+ .streams_enable = true,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY3 */
+ {
+ .regulators = {
+ { .supply = "vdda-phy", .init_load_uA = 15900 },
+ { .supply = "vdda-pll", .init_load_uA = 8900 }
+ },
+ .clock = { "csiphy_rx", "csiphy3", "csiphy3_timer" },
+ .clock_rate = {
+ { 400000000 },
+ { 0 },
+ { 400000000 },
+ },
+ .reg = { "csiphy3" },
+ .interrupt = { "csiphy3" },
+ .csiphy = {
+ .id = 3,
+ .streams_enable = true,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+};
+
+static const struct camss_ife_stream csid_ife_streams_sa8775p_pix[] = {
+ { .id = 0, .pipe = CAMSS_IFE_HW_PIPE_RDI0 },
+ { .id = 1, .pipe = CAMSS_IFE_HW_PIPE_RDI1 },
+ { .id = 2, .pipe = CAMSS_IFE_HW_PIPE_RDI2 },
+ { .id = 3, .pipe = CAMSS_IFE_HW_PIPE_PP },
+};
+
+static const struct camss_ife_stream csid_ife_lite_streams_sa8775p_pix[] = {
+ { .id = 0, .pipe = CAMSS_IFE_HW_PIPE_RDI0 },
+ { .id = 1, .pipe = CAMSS_IFE_HW_PIPE_RDI1 },
+ { .id = 2, .pipe = CAMSS_IFE_HW_PIPE_RDI2 },
+ { .id = 3, .pipe = CAMSS_IFE_HW_PIPE_RDI3 },
+};
+
+static const struct camss_subdev_resources csid_res_sa8775p_pix[] = {
+ /* CSID0 */
+ {
+ .regulators = {},
+ .clock = { "csid", "csiphy_rx" },
+ .clock_rate = { { 400000000 }, { 400000000 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .streams_enable = true,
+ .source_streams_mode = CSID_STREAMS_SINGLE_PAD,
+ .hw_ops = &csid_ops_gen3,
+ .parent_dev_ops = &ife_parent_dev_ops,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID1 */
+ {
+ .regulators = {},
+ .clock = { "csid", "csiphy_rx" },
+ .clock_rate = { { 400000000 }, { 400000000 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .streams_enable = true,
+ .source_streams_mode = CSID_STREAMS_SINGLE_PAD,
+ .hw_ops = &csid_ops_gen3,
+ .parent_dev_ops = &ife_parent_dev_ops,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID_LITE0 */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 400000000 }, { 400000000 } },
+ .reg = { "csid_lite0" },
+ .interrupt = { "csid_lite0" },
+ .csid = {
+ .is_lite = true,
+ .streams_enable = true,
+ .source_streams_mode = CSID_STREAMS_SINGLE_PAD,
+ .hw_ops = &csid_ops_gen3,
+ .parent_dev_ops = &ife_parent_dev_ops,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID_LITE1 */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 400000000 }, { 400000000 } },
+ .reg = { "csid_lite1" },
+ .interrupt = { "csid_lite1" },
+ .csid = {
+ .is_lite = true,
+ .streams_enable = true,
+ .source_streams_mode = CSID_STREAMS_SINGLE_PAD,
+ .hw_ops = &csid_ops_gen3,
+ .parent_dev_ops = &ife_parent_dev_ops,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID_LITE2 */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 400000000 }, { 400000000 } },
+ .reg = { "csid_lite2" },
+ .interrupt = { "csid_lite2" },
+ .csid = {
+ .is_lite = true,
+ .streams_enable = true,
+ .source_streams_mode = CSID_STREAMS_SINGLE_PAD,
+ .hw_ops = &csid_ops_gen3,
+ .parent_dev_ops = &ife_parent_dev_ops,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID_LITE3 */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 400000000 }, { 400000000 } },
+ .reg = { "csid_lite3" },
+ .interrupt = { "csid_lite3" },
+ .csid = {
+ .is_lite = true,
+ .streams_enable = true,
+ .source_streams_mode = CSID_STREAMS_SINGLE_PAD,
+ .hw_ops = &csid_ops_gen3,
+ .parent_dev_ops = &ife_parent_dev_ops,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID_LITE4 */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 400000000 }, { 400000000 } },
+ .reg = { "csid_lite4" },
+ .interrupt = { "csid_lite4" },
+ .csid = {
+ .is_lite = true,
+ .streams_enable = true,
+ .source_streams_mode = CSID_STREAMS_SINGLE_PAD,
+ .hw_ops = &csid_ops_gen3,
+ .parent_dev_ops = &ife_parent_dev_ops,
+ .formats = &csid_formats_gen2,
+ },
+ },
+};
+
+static const struct camss_subdev_resources ife_res_sa8775p_pix[] = {
+ /* IFE0 */
+ {
+ .regulators = {},
+ .clock = { "cpas_vfe0", "vfe0", "vfe0_fast_ahb",
+ "cpas_ahb", "gcc_axi_hf", "cpas_fast_ahb_clk",
+ "camnoc_axi" },
+ .clock_rate = {
+ { 0 },
+ { 480000000 },
+ { 300000000, 400000000 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 300000000, 400000000 },
+ { 400000000 },
+ },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .ife = {
+ .type = CAMSS_IFE_SUBDEV_TYPE_IFE,
+ .pads = &ife_pads_v41x,
+ .top_ops = &ife_top_v41x_ops,
+ .buswr_ops = &ife_buswr_31x_ops,
+ .mod_ops = &ife_mod_v41x_ops,
+ .num_sink_streams = ARRAY_SIZE(csid_ife_streams_sa8775p_pix),
+ .sink_streams = csid_ife_streams_sa8775p_pix,
+ },
+ },
+ /* IFE1 */
+ {
+ .regulators = {},
+ .clock = { "cpas_vfe1", "vfe1", "vfe1_fast_ahb",
+ "cpas_ahb", "gcc_axi_hf", "cpas_fast_ahb_clk",
+ "camnoc_axi" },
+ .clock_rate = {
+ { 0 },
+ { 480000000 },
+ { 300000000, 400000000 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 300000000, 400000000 },
+ { 400000000 },
+ },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .ife = {
+ .type = CAMSS_IFE_SUBDEV_TYPE_IFE,
+ .pads = &ife_pads_v41x,
+ .top_ops = &ife_top_v41x_ops,
+ .buswr_ops = &ife_buswr_31x_ops,
+ .mod_ops = &ife_mod_v41x_ops,
+ .num_sink_streams = ARRAY_SIZE(csid_ife_streams_sa8775p_pix),
+ .sink_streams = csid_ife_streams_sa8775p_pix,
+ },
+ },
+ /* IFE_LITE0 */
+ {
+ .regulators = {},
+ .clock = { "cpas_ahb", "cpas_vfe_lite", "vfe_lite_ahb",
+ "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite",
+ "gcc_axi_hf", "camnoc_axi" },
+ .clock_rate = {
+ { 0 },
+ { 0 },
+ { 300000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 480000000, 600000000, 600000000, 600000000 },
+ { 0 },
+ { 400000000 },
+ },
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .ife = {
+ .type = CAMSS_IFE_SUBDEV_TYPE_IFE_LITE,
+ .pads = &ife_lite_pads_v30x,
+ .top_ops = &ife_lite_top_30x_ops,
+ .buswr_ops = &ife_buswr_31x_ops,
+ .num_sink_streams = ARRAY_SIZE(csid_ife_lite_streams_sa8775p_pix),
+ .sink_streams = csid_ife_lite_streams_sa8775p_pix,
+ },
+ },
+ /* IFE_LITE1 */
+ {
+ .regulators = {},
+ .clock = { "cpas_ahb", "cpas_vfe_lite", "vfe_lite_ahb",
+ "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite",
+ "gcc_axi_hf", "camnoc_axi" },
+ .clock_rate = {
+ { 0 },
+ { 0 },
+ { 300000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 480000000, 600000000, 600000000, 600000000 },
+ { 0 },
+ { 400000000 },
+ },
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .ife = {
+ .type = CAMSS_IFE_SUBDEV_TYPE_IFE_LITE,
+ .pads = &ife_lite_pads_v30x,
+ .top_ops = &ife_lite_top_30x_ops,
+ .buswr_ops = &ife_buswr_31x_ops,
+ .num_sink_streams = ARRAY_SIZE(csid_ife_lite_streams_sa8775p_pix),
+ .sink_streams = csid_ife_lite_streams_sa8775p_pix,
+ },
+ },
+ /* IFE_LITE2 */
+ {
+ .regulators = {},
+ .clock = { "cpas_ahb", "cpas_vfe_lite", "vfe_lite_ahb",
+ "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite",
+ "gcc_axi_hf", "camnoc_axi" },
+ .clock_rate = {
+ { 0 },
+ { 0 },
+ { 300000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 480000000, 600000000, 600000000, 600000000 },
+ { 0 },
+ { 400000000 },
+ },
+ .reg = { "vfe_lite2" },
+ .interrupt = { "vfe_lite2" },
+ .ife = {
+ .type = CAMSS_IFE_SUBDEV_TYPE_IFE_LITE,
+ .pads = &ife_lite_pads_v30x,
+ .top_ops = &ife_lite_top_30x_ops,
+ .buswr_ops = &ife_buswr_31x_ops,
+ .num_sink_streams = ARRAY_SIZE(csid_ife_lite_streams_sa8775p_pix),
+ .sink_streams = csid_ife_lite_streams_sa8775p_pix,
+ },
+ },
+ /* IFE_LITE3 */
+ {
+ .regulators = {},
+ .clock = { "cpas_ahb", "cpas_vfe_lite", "vfe_lite_ahb",
+ "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite",
+ "gcc_axi_hf", "camnoc_axi" },
+ .clock_rate = {
+ { 0 },
+ { 0 },
+ { 300000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 480000000, 600000000, 600000000, 600000000 },
+ { 0 },
+ { 400000000 },
+ },
+ .reg = { "vfe_lite3" },
+ .interrupt = { "vfe_lite3" },
+ .ife = {
+ .type = CAMSS_IFE_SUBDEV_TYPE_IFE_LITE,
+ .pads = &ife_lite_pads_v30x,
+ .top_ops = &ife_lite_top_30x_ops,
+ .buswr_ops = &ife_buswr_31x_ops,
+ .num_sink_streams = ARRAY_SIZE(csid_ife_lite_streams_sa8775p_pix),
+ .sink_streams = csid_ife_lite_streams_sa8775p_pix,
+ },
+ },
+ /* IFE_LITE4 */
+ {
+ .regulators = {},
+ .clock = { "cpas_ahb", "cpas_vfe_lite", "vfe_lite_ahb",
+ "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite",
+ "gcc_axi_hf", "camnoc_axi" },
+ .clock_rate = {
+ { 0 },
+ { 0 },
+ { 300000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 480000000, 600000000, 600000000, 600000000 },
+ { 0 },
+ { 400000000 },
+ },
+ .reg = { "vfe_lite4" },
+ .interrupt = { "vfe_lite4" },
+ .ife = {
+ .type = CAMSS_IFE_SUBDEV_TYPE_IFE_LITE,
+ .pads = &ife_lite_pads_v30x,
+ .top_ops = &ife_lite_top_30x_ops,
+ .buswr_ops = &ife_buswr_31x_ops,
+ .num_sink_streams = ARRAY_SIZE(csid_ife_lite_streams_sa8775p_pix),
+ .sink_streams = csid_ife_lite_streams_sa8775p_pix,
+ },
+ },
+};
+
static const struct resources_icc icc_res_qcs8300[] = {
{
.name = "ahb",
@@ -6275,6 +6681,23 @@ static const struct camss_resources sa8775p_resources = {
.icc_path_num = ARRAY_SIZE(icc_res_sa8775p),
};
+static const struct camss_resources sa8775p_pix_resources = {
+ .version = CAMSS_8775P,
+ .csiphy_res = csiphy_res_sa8775p_pix,
+ .tpg_res = tpg_res_8775p,
+ .csid_res = csid_res_sa8775p_pix,
+ .csid_wrapper_res = &csid_wrapper_res_sm8550,
+ .ife_res = ife_res_sa8775p_pix,
+ .icc_res = icc_res_sa8775p,
+ .icc_path_num = ARRAY_SIZE(icc_res_sa8775p),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_sa8775p_pix),
+ .tpg_num = ARRAY_SIZE(tpg_res_8775p),
+ .csid_num = ARRAY_SIZE(csid_res_sa8775p_pix),
+ .ife_num = 2,
+ .ife_lite_num = 5,
+ .link_entities = camss_ife_link_entities
+};
+
static const struct camss_resources sdm660_resources = {
.version = CAMSS_660,
.csiphy_res = csiphy_res_660,
@@ -6449,6 +6872,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,sm6150-camss", .data = &sm6150_resources },
{ .compatible = "qcom,sm6350-camss", .data = &sm6350_resources },
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
+ { .compatible = "qcom,sa8775p-camss-pix", .data = &sa8775p_pix_resources },
{ .compatible = "qcom,sm8250pix-camss", .data = &sm8250pix_resources },
{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
--
2.34.1