Re: [RFC PATCH v2 3/7] dt-bindings: net: amlogic,meson-dwmac: add amlogic,t7-dwmac
From: Lucas Tanure
Date: Wed Oct 07 2026 - 07:02:59 EST
On Wed, Oct 7, 2026 at 10:51 AM Conor Dooley <conor@xxxxxxxxxx> wrote:
>
> On Wed, Oct 07, 2026 at 09:26:23AM +0100, Lucas Tanure wrote:
> > The T7 has the same ethernet glue as the G12A, but the controller
> > reaches memory through a pipeline stage that this SoC inserts in the
> > bus path. That stage has a gate of its own, which no other member of
> > the family has, and nothing else in Linux claims it. It is therefore
> > switched off as unused, and the port can then no longer finish a
> > transfer.
> >
> > Describing it needs a fourth clock, and the fourth clock of the
> > existing list drives the timing adjustment logic, which the T7 never
> > uses. So the T7 gets a list of its own with the gate in that place,
> > under the name the SD and eMMC controllers already use.
> >
> > Assisted-by: LLM
> > Signed-off-by: Lucas Tanure <tanure@xxxxxxxxx>
>
> Didn't I ack the previous version?
Sorry, I didn't receive one.
>
> What changed?
Nothing.
>
> Thanks,
> Conor.
>
> > ---
> > .../bindings/net/amlogic,meson-dwmac.yaml | 47 +++++++++++++++++++
> > 1 file changed, 47 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
> > index 90ef79161ab1..96118b4d1560 100644
> > --- a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
> > +++ b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
> > @@ -23,6 +23,7 @@ select:
> > - amlogic,meson-gxbb-dwmac
> > - amlogic,meson-axg-dwmac
> > - amlogic,meson-g12a-dwmac
> > + - amlogic,t7-dwmac
> > required:
> > - compatible
> >
> > @@ -57,6 +58,47 @@ allOf:
> > - const: clkin1
> > - const: timing-adjustment
> >
> > + # The T7 applies the RGMII RX delay through PRG_ETH1 and never enables the
> > + # timing adjustment logic, so it has no timing-adjustment clock. What it does
> > + # need is the gate of the pipeline stage the controller reaches DRAM through.
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: amlogic,t7-dwmac
> > + then:
> > + properties:
> > + clocks:
> > + items:
> > + - description: GMAC main clock
> > + - description: First parent clock of the internal mux
> > + - description: Second parent clock of the internal mux
> > + - description:
> > + clock of the pipeline stage inserted in the bus path between
> > + the controller and the DRAM. Without it, the controller cannot
> > + complete DMA transfers.
> > +
> > + clock-names:
> > + items:
> > + - const: stmmaceth
> > + - const: clkin0
> > + - const: clkin1
> > + - const: pipeline
> > +
> > + # Delay definitions for Meson8b and newer (including T7)
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - amlogic,meson8b-dwmac
> > + - amlogic,meson8m2-dwmac
> > + - amlogic,meson-gxbb-dwmac
> > + - amlogic,meson-axg-dwmac
> > + - amlogic,meson-g12a-dwmac
> > + - amlogic,t7-dwmac
> > + then:
> > + properties:
> > amlogic,tx-delay-ns:
> > enum: [0, 2, 4, 6]
> > default: 2
> > @@ -106,6 +148,7 @@ allOf:
> > contains:
> > enum:
> > - amlogic,meson-g12a-dwmac
> > + - amlogic,t7-dwmac
> > then:
> > properties:
> > rx-internal-delay-ps:
> > @@ -143,6 +186,10 @@ properties:
> > - amlogic,meson6-dwmac
> > - amlogic,meson8m2-dwmac
> > - const: snps,dwmac
> > + - items:
> > + - const: amlogic,t7-dwmac
> > + - const: snps,dwmac-5.10a
> > + - const: snps,dwmac
> >
> > reg:
> > items:
> > --
> > 2.56.0
> >