Re: [PATCH v3 5/5] phy: qcom-qmp-ufs: Add Glymur support

[Dmitry Baryshkov]

On Wed, Oct 07, 2026 at 05:03:02PM +0530, Pradeep Pragallapati wrote:
> 
> 
> On 10/7/2026 1:18 PM, Dmitry Baryshkov wrote:
> > On Wed, Oct 07, 2026 at 11:59:38AM +0530, Pradeep P V K wrote:
> >> Add the init sequence tables and config for the UFS QMP phy found in
> >> the Glymur SoC.
> >>
> >> Reviewed-by: Abel Vesa <abel.vesa@xxxxxxxxxxxxxxxx>
> >> Acked-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
> >> Signed-off-by: Pradeep P V K <pradeep.pragallapati@xxxxxxxxxxxxxxxx>
> >> ---
> >>  drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 99 +++++++++++++++++++++++++++++++++
> >>  1 file changed, 99 insertions(+)
> >>
> >> +	.offsets		= &qmp_ufs_offsets_v6,
> > 
> > So, is it a PHY using v6 offsets, but v7 registers inside?
> > 
> The QSERDES RX0 register offsets on Glymur SoC are aligned with the v7 register layout offsets.
> Therefore, the v7 QSERDES RX0 register offsets are used for Glymur (similar to SM8750).

Mention in the commit message, please.

> 
> >> +	.max_supported_gear	= UFS_HS_G5,
> >> +
> >> +	.vreg_list		= glymur_ufsphy_vreg_l,
> >> +	.num_vregs		= ARRAY_SIZE(glymur_ufsphy_vreg_l),
> >> +	.regs			= ufsphy_v6_regs_layout,
> > 
> > v7

This still holds.

> > 
> >> +};
> >> +
> >>  static const struct qmp_phy_cfg milos_ufsphy_cfg = {
> >>  	.lanes			= 2,
> >>  
> > 
> 
> 
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-- 
With best wishes
Dmitry