[PATCH 0/4] drm/msm/dpu: fix pipe ordering for source-split planes

[Mahadevan P]

Virtual planes can use two SSPPs when a plane exceeds the single-pipe
width or clock limit and parallel multirect cannot be used. The pair
can contain different SSPP types, depending on resource availability.

This series handles source split ordering for those pairs:

1. Keep the higher priority SSPP on the left before DPU 5.0.
2. Add the SRC_SPLIT_ORDER operation for DPU 5.0 through 12.x.
3. Program the order from the destination X positions, clearing the bit
   for the left source and sources without a sibling.
4. Add the operation for the DPU 13.x SSPP rectangle banks.

Assisted-by: LLM
Signed-off-by: Mahadevan P <mahadevan.p@xxxxxxxxxxxxxxxx>
---
Mahadevan P (4):
      drm/msm/dpu: keep SSPP priority order for split planes on DPU < 5.0
      drm/msm/dpu: add SSPP op to program the source split order
      drm/msm/dpu: program the source split order for split planes
      drm/msm/dpu: add source split order op for DPU 13.x

 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c        | 19 ++++++++++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c     | 35 +++++++++++++++++++++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h     | 11 ++++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c | 14 ++++++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c       |  4 +++
 5 files changed, 83 insertions(+)
---
base-commit: aac26bee2287c88af5be5a5ff96d783b19a28790
change-id: 20261009-pipe_order-87a83717ac4c

Best regards,
-- 
Mahadevan P <mahadevan.p@xxxxxxxxxxxxxxxx>