[PATCH v15 00/16] PCI/CXL: Add CXL reset support for Type 2 devices

[Srirangan Madhavan]

Hi folks,

This series adds CXL Reset for Type 2 devices through the existing PCI
reset_method and reset sysfs attributes. It disables CXL.cache, performs
supported cache writeback, initiates CXL Reset with Memory Clear, and
restores cached HDM decoder and CXL Device DVSEC state before PCI use
resumes. Active HDM ranges are reserved and CPU caches invalidated before
and after reset. The method remains limited to eligible single-function
devices with both CXL.cache and CXL.mem enabled.

The reset sequence follows the CXL 4.0 specification [3], including
CXL.cache disable, optional cache writeback, CXL Reset Memory Clear,
ResetComplete polling, and ResetError reporting. Sections 9.7.2 and 9.7.3
define the completion timeout encodings and reset access restrictions.

The userspace ABI is the existing PCI reset interface:

    /sys/bus/pci/devices/.../reset_method
    /sys/bus/pci/devices/.../reset

Userspace selects "cxl_reset" in reset_method and triggers the reset
through reset. Following Dan's v6 feedback, this uses the PCI interface
instead of adding a memdev-specific sysfs ABI.

For sysfs reset, the generic PCI path invokes the driver's reset_prepare()
callback when provided and disables PCI I/O, memory decoding, and bus
mastering. The CXL path reserves affected HDM ranges exclusively and
blocks IOMMU translations where applicable. It does not offline memory
or revoke mappings; it relies on CXL.mem users retaining conflicting
iomem resources while access remains active.

Changes from v14 [1]:
- Build HDM register helpers directly from CXL_BUS and move cxl_rwsem
  with the first built-in cache/state users, following Dave's reference.
- Split PCI-facing reset and discovery code from the generic HDM register
  and state helpers, following review of the CXL/PCI boundary.
- Rework decoder settings and cache refresh so the HDM layer does not
  depend on PCI devices, while retaining the tools/testing/cxl build.
- Skip PCI HDM cache checks and refresh for DVSEC-emulated decoders,
  and retain cached global control when register reads return all ones.
- Share DVSEC HDM-count validation, cache the Device DVSEC offset for
  restoration, and report every PCI_COMMAND restore failure during cache init.
- Reject DVSEC-only memory decode, whose ranges are not in the HDM cache.
- Use the documented region-quiesce API with explicit lock annotations.
- Capture the private HDM snapshot with range preparation and use that
  same snapshot for restoration.
- Reject CXL reset and CXL bus reset requiring state restoration when no
  PCI state has been saved, before changing the device.
- Fold the separate HDM range-overflow check into register unpacking and
  reduce the production changes to 15 patches. A separate final patch adds
  seven HDM decoder checks run separately from the watermark hooks under
  tools/testing/cxl/.

The CXL.cache/CXL.mem eligibility policy is unchanged from v14.

CXL Reset requires a registered CPU cache clean/invalidate provider
and matching firmware, such as the separate SMCCC provider series [2].
Without that provider, cxl_reset can be advertised while execution returns
-ENOTTY. The mock regression suite uses its test-only invalidation bypass.

The cxl_test module checks HDM range boundaries, zero-size and
uncommitted state, lock and target-type decoding, and 12-way interleave.
All seven checks and all 16 ndctl CXL regression tests passed on an ARM64
target with 4 KiB pages, with a separate ndctl test log-collection race
fix.

[1] https://lore.kernel.org/linux-cxl/20261001092227.3004747-1-smadhavan@xxxxxxxxxx/
[2] https://lore.kernel.org/all/20260910082142.1522865-1-smadhavan@xxxxxxxxxx/T/
[3] https://computeexpresslink.org/wp-content/uploads/2026/02/CXL-Specification_rev4p0_ver1p0_2026February26_clean_evalcopy_v2.pdf

Srirangan Madhavan (16):
  cxl: Drop stale decoder interleave limit comment
  cxl: Share CXL port upstream PCI device lookup
  cxl: Move decoder declarations to shared header
  cxl: Embed decoder configuration in a standalone structure
  cxl: Introduce endpoint HDM decoder settings
  cxl: Move HDM decoder helpers to built-in code
  cxl: Share HDM decoder register unpacking
  cxl: Refresh cached PCI HDM decoder settings
  PCI/CXL: Cache endpoint HDM state during PCI enumeration
  PCI/CXL: Add CXL Device Reset sequencing
  cxl: Validate and synchronize HDM ranges around reset
  PCI/CXL: Reject reset with unsafe function scope
  PCI/CXL: Restore CXL state after PCI reset
  PCI/CXL: Expose CXL Reset as a PCI reset method
  PCI/CXL: Restore CXL state after CXL bus reset
  tools/testing/cxl: Add HDM decoder range checks

 MAINTAINERS                       |   1 +
 drivers/cxl/Kconfig               |   5 +
 drivers/cxl/acpi.c                |  26 +-
 drivers/cxl/core/Makefile         |   2 +-
 drivers/cxl/core/atl.c            |   4 +-
 drivers/cxl/core/core.h           |  15 +
 drivers/cxl/core/hdm.c            | 282 +++++------
 drivers/cxl/core/hdm_regs.c       | 455 ++++++++++++++++++
 drivers/cxl/core/hdm_state.c      | 367 +++++++++++++++
 drivers/cxl/core/pci.c            | 111 ++++-
 drivers/cxl/core/port.c           |  68 ++-
 drivers/cxl/core/region.c         | 102 ++--
 drivers/cxl/core/regs.c           |   9 +
 drivers/cxl/cxl.h                 |  46 +-
 drivers/cxl/pci.c                 |   2 +-
 drivers/cxl/port.c                |   4 +-
 drivers/pci/Makefile              |   1 +
 drivers/pci/bus.c                 |   1 +
 drivers/pci/cxl.c                 | 747 ++++++++++++++++++++++++++++++
 drivers/pci/pci.c                 |  18 +
 drivers/pci/pci.h                 |  29 ++
 drivers/pci/probe.c               |   1 +
 include/cxl/cxl.h                 |  59 ++-
 include/cxl/hdm.h                 | 105 +++++
 include/cxl/pci.h                 |  13 +
 include/linux/pci.h               |   8 +-
 include/uapi/linux/pci_regs.h     |  14 +
 tools/testing/cxl/Kbuild          |   1 -
 tools/testing/cxl/cxl_core_test.c |  78 ++++
 tools/testing/cxl/cxl_core_test.h |   8 +
 tools/testing/cxl/test/cxl.c      | 163 +++----
 31 files changed, 2343 insertions(+), 402 deletions(-)
 create mode 100644 drivers/cxl/core/hdm_regs.c
 create mode 100644 drivers/cxl/core/hdm_state.c
 create mode 100644 drivers/pci/cxl.c
 create mode 100644 include/cxl/hdm.h
 create mode 100644 tools/testing/cxl/cxl_core_test.h


base-commit: fef22d37d47043b63e4007f2f5fe762fa21fae0c
-- 
2.43.0