RE: [PATCH iwl-net 1/2] ice: fix DPLL registration on boards without the SMA clock mux

[Nowlin, Alexander]

> -----Original Message-----
> From: Petr Oros <poros@xxxxxxxxxx> 
> Sent: Thursday, September 17, 2026 12:03 PM
> To: netdev@xxxxxxxxxxxxxxx
> Cc: Oros, Petr <poros@xxxxxxxxxx>; stable@xxxxxxxxxxxxxxx; Nguyen, Anthony L <anthony.l.nguyen@xxxxxxxxx>; Kitszel, Przemyslaw <przemyslaw.kitszel@xxxxxxxxx>; Andrew Lunn <andrew+netdev@xxxxxxx>; > David S. Miller <davem@xxxxxxxxxxxxx>; Eric Dumazet <edumazet@xxxxxxxxxx>; Jakub Kicinski <kuba@xxxxxxxxxx>; Paolo Abeni <pabeni@xxxxxxxxxx>; Simon Horman <horms@xxxxxxxxxx>; Kubalewski, Arkadiusz <arkadiusz.kubalewski@xxxxxxxxx>; intel-wired-lan@xxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx
> Subject: [PATCH iwl-net 1/2] ice: fix DPLL registration on boards without the SMA clock mux
> 
> The SMA and U.FL connectors of an E810-C timing board are routed by a
> PCA9575 GPIO expander, and ice_dpll_init_info_sw_pins() reaches it through ice_read_sma_ctrl(). On a board that carries a CGU but no such expander the netlist lookup fails with -ENXIO, which aborts
> ice_dpll_init_info() and with it the whole DPLL registration:
> 
>   ice 0000:cc:00.0: ice_dpll_init_info - fail: d->inputs:...
>   ice 0000:cc:00.0: DPLLs init failure err:-6
> 
> Userspace loses the EEC and PPS devices, every CGU pin and the recovered clock pin.
> 
> The netlist describes the mux with a clock mux node, which
> ice_init_feature_support() already turns into ICE_F_SMA_CTRL. Key the software controlled pins on that flag. Without the mux the SMA wrappers stay inputs, the state the mux path programs at init anyway, and > do not advertise DIRECTION_CAN_CHANGE. The U.FL pins are the other leg of the mux, so they are hidden, and the outgoing CGU pins stay visible as
> REF-SMA1 and REF-SMA2/U.FL2.
> 
> The layout is not exotic, the E810_C827_SyncE_SFP_SEC configuration in Intel's 4.80 NVM package has no clock mux node either. Such boards worked until the SMA and U.FL redesign moved the expander access > into the DPLL init path.
> 
> Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Petr Oros <poros@xxxxxxxxxx>
> ---
>  drivers/net/ethernet/intel/ice/ice_dpll.c | 20 +++++++++++++++++---
>  1 file changed, 17 insertions(+), 3 deletions(-)

Tested-by: Alexander Nowlin <alexander.nowlin@xxxxxxxxx>