[PATCH v2 1/4] dt-bindings: power: mediatek: Add the MT8188 access controllers

From: Michał Kopeć

Date: Sun Oct 11 2026 - 14:48:55 EST


On MT8188 the GPU timestamp counter only counts once a register in the
MFGCFG block feeds it the SoC system timer. MFGCFG loses that setting
whenever the MFG1 power domain is turned off, so the power controller
has to restore it after powering the domain on, and needs access to
MFGCFG for that.

Describe the blocks that the MT8188 power controller accesses,
INFRACFG_AO for bus protection and MFGCFG, and extend the description
of access-controllers to cover blocks with settings to restore.

Signed-off-by: Michał Kopeć <michal@nozomi.space>
---
.../power/mediatek,power-controller.yaml | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index d03e4a9251635..8d96cde7c1a51 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -54,7 +54,8 @@ properties:
description:
A number of phandles to external blocks to set and clear the required
bits to enable or disable bus protection, necessary to avoid any bus
- faults while enabling or disabling a power domain.
+ faults while enabling or disabling a power domain, or to restore
+ settings that a block loses when its power domain is turned off.
For example, this may hold phandles to INFRACFG and SMI.
minItems: 1
maxItems: 6
@@ -188,6 +189,19 @@ allOf:
minItems: 2
maxItems: 2

+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt8188-power-controller
+ then:
+ properties:
+ access-controllers:
+ items:
+ - description: handle to INFRACFG_AO register block
+ - description: handle to MFGCFG register block
+
- if:
properties:
compatible:
--
2.56.0