Re: [PATCH v8 4/4] phy: ti-pipe3: Fix clock leaks in init/exit error paths

[Manivannan Sadhasivam]

On Wed, Sep 09, 2026 at 08:26:30PM +0800, Hongling Zeng wrote:
> Two paths return without disabling the clocks that ti_pipe3_init()
> has just enabled, leaking clock enable references:
> 
> 1. In ti_pipe3_init(), when regmap_update_bits() fails for PCIe mode,
>    the function returns the error without calling
>    ti_pipe3_disable_clocks(). The clocks stay permanently enabled
>    since the PHY framework won't invoke the .exit callback on init
>    failure.
> 
> 2. In ti_pipe3_exit(), when the PHY is in SATA mode without
>    dpll_reset_syscon, the function returns 0 early to avoid powering
>    down the SATA DPLL (Errata i783), which also skips the
>    ti_pipe3_disable_clocks() at the end of the function. Every
>    init/exit cycle therefore leaks the clock enable reference taken
>    in ti_pipe3_init().
> 
> Fix both by adding the missing ti_pipe3_disable_clocks() calls,
> consistent with how the DPLL program error path handles cleanup.
> 
> Fixes: 234738ea3390 ("phy: ti-pipe3: move clk initialization to a separate function")
> Fixes: 0a0830feb2ad ("phy: ti-pipe3: fix suspend")
> Cc: stable@xxxxxxxxxxxxxxx

This is not really a stable candidate...

> Reported-by: Sashiko AI <sashiko@xxxxxxxxxx>
> Closes: https://lore.kernel.org/all/20260518023657.41852C2BCB0@xxxxxxxxxxxxxxx/
> Signed-off-by: Hongling Zeng <zenghongling@xxxxxxxxxx>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxxxxxxxx>

- Mani

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