[PATCH RFC v3 5/8] drm/i915/display/dp: Use dp_connector helpers to expose link training state
From: Kory Maincent
Date: Mon Oct 12 2026 - 11:30:58 EST
Adopt the new DRM core DisplayPort helpers, which expose source and sink
capabilities along with the maximum and current link parameters to
userspace through the dp_link/ sysfs attributes.
Keep the sink's supported link rates unclamped in the new
dpcd_sink_rates/num_dpcd_sink_rates fields, rather than limiting them to
the rates the source supports.
Signed-off-by: Kory Maincent <kory.maincent@xxxxxxxxxxx>
---
Changes in v3:
- Move the call to new helpers around.
- Use real sink rates instead of the modified ones.
Changes in v2:
- Remove voltage swing and pre emphasis properties.
---
drivers/gpu/drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 55 +++++++++++++++++++++-
.../gpu/drm/i915/display/intel_dp_link_training.c | 14 ++++++
3 files changed, 69 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5f0fe18c0614e..025523ae58e6c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1845,6 +1845,8 @@ struct intel_dp {
/* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
int num_sink_rates;
int sink_rates[DP_MAX_SUPPORTED_RATES];
+ int num_dpcd_sink_rates;
+ int dpcd_sink_rates[DP_MAX_SUPPORTED_RATES];
bool use_rate_select;
/* Max sink lane count as reported by DP_MAX_LANE_COUNT */
int max_sink_lane_count;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b769723a1c0fd..6af59e75bd666 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -189,6 +189,7 @@ static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
{
intel_dp->sink_rates[0] = 162000;
intel_dp->num_sink_rates = 1;
+ intel_dp->num_dpcd_sink_rates = 0;
}
/* update sink rates from dpcd */
@@ -203,10 +204,14 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
intel_dp->lttpr_common_caps,
&intel_dp->desc,
intel_dp->tunnel,
- intel_dp->sink_rates);
+ intel_dp->dpcd_sink_rates);
if (num_sink_rates < 0)
num_sink_rates = 0;
+ intel_dp->num_dpcd_sink_rates = num_sink_rates;
+ memcpy(intel_dp->sink_rates, intel_dp->dpcd_sink_rates,
+ sizeof(int) * num_sink_rates);
+
/*
* Don't limit the rates of sinks with the 3.24 Gbps DPCD quirk
* (needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panels),
@@ -4646,10 +4651,14 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
num_sink_rates = drm_dp_read_edp_sink_rates(&intel_dp->aux,
intel_dp->edp_dpcd[0],
- intel_dp->sink_rates);
+ intel_dp->dpcd_sink_rates);
if (num_sink_rates < 0)
num_sink_rates = 0;
+ intel_dp->num_dpcd_sink_rates = num_sink_rates;
+ memcpy(intel_dp->sink_rates, intel_dp->dpcd_sink_rates,
+ sizeof(int) * num_sink_rates);
+
/*
* Some platforms cannot reliably drive HBR3 rates due to PHY limitations,
* even if the sink advertises support. Reject any sink rates above HBR2 on
@@ -6188,6 +6197,20 @@ void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external)
intel_dp_needs_dpcd_probe(intel_dp, force_on_external));
}
+static void intel_dp_set_sink_caps(struct intel_connector *connector,
+ struct intel_dp *intel_dp)
+{
+ struct drm_connector_dp_link_caps link_caps;
+
+ link_caps.nlanes = drm_dp_get_max_lane_count(intel_dp->dpcd,
+ intel_dp->lttpr_common_caps);
+ link_caps.link_rates = intel_dp->dpcd_sink_rates;
+ link_caps.nlink_rates = intel_dp->num_dpcd_sink_rates;
+ link_caps.dsc = drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
+
+ drm_dp_sink_set_caps(&connector->base, &link_caps);
+}
+
static int
intel_dp_detect(struct drm_connector *_connector,
struct drm_modeset_acquire_ctx *ctx,
@@ -6259,6 +6282,8 @@ intel_dp_detect(struct drm_connector *_connector,
intel_dp_tunnel_uhbr_lanes_wa_reset(intel_dp);
+ drm_dp_sink_reset_caps(_connector);
+
goto out_unset_edid;
}
@@ -6290,6 +6315,8 @@ intel_dp_detect(struct drm_connector *_connector,
intel_dp_print_rates(intel_dp);
+ intel_dp_set_sink_caps(connector, intel_dp);
+
if (intel_dp->is_mst) {
/*
* If we are in MST mode then this connector
@@ -7037,11 +7064,14 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
struct intel_connector *connector)
{
struct intel_display *display = to_intel_display(dig_port);
+ struct drm_connector_dp_link_caps link_caps;
struct intel_dp *intel_dp = &dig_port->dp;
struct intel_encoder *encoder = &dig_port->base;
struct drm_device *dev = encoder->base.dev;
enum port port = encoder->port;
+ int *rates;
int type;
+ int ret;
if (drm_WARN(dev, dig_port->max_lanes < 1,
"Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
@@ -7116,6 +7146,27 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
intel_dp_set_common_link_params(intel_dp);
intel_dp_reset_link_params(intel_dp);
+ rates = kmemdup_array(intel_dp->source_rates,
+ intel_dp->num_source_rates,
+ sizeof(*rates),
+ GFP_KERNEL);
+ if (!rates) {
+ intel_dp_aux_fini(intel_dp);
+ goto fail;
+ }
+
+ link_caps.nlanes = dig_port->max_lanes;
+ link_caps.nlink_rates = intel_dp->num_source_rates;
+ link_caps.link_rates = rates;
+ link_caps.dsc = HAS_DSC(display);
+
+ ret = drm_dp_source_set_caps(&connector->base, &link_caps);
+ if (ret)
+ drm_dbg_kms(display->drm,
+ "failed to set source link rates, skipping.\n");
+
+ kfree(rates);
+
/* init MST on ports that can support it */
intel_dp_mst_encoder_init(dig_port, connector->base.base.id);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index cb92cff906146..c77cb124f1419 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1758,6 +1758,18 @@ static void link_recovery_reset(struct intel_dp_link_training *link_training)
link_training->recovery_state = INTEL_DP_LINK_RECOVERY_IDLE;
}
+static void intel_dp_report_link_train(struct intel_dp *intel_dp)
+{
+ struct intel_connector *connector = intel_dp->attached_connector;
+
+ if (!connector)
+ return;
+
+ drm_dp_set_cur_link_params(&connector->base, intel_dp->link_rate,
+ intel_dp->lane_count,
+ connector->dp.dsc_decompression_enabled);
+}
+
/**
* intel_dp_stop_link_train - stop link training
* @intel_dp: DP struct
@@ -1787,6 +1799,8 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp,
intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
DP_TRAINING_PATTERN_DISABLE);
+ intel_dp_report_link_train(intel_dp);
+
if (intel_dp_is_uhbr(crtc_state)) {
ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state),
ret == 0,
--
2.43.0