[PATCH 1/2] riscv: dts: spacemit: k1: mark boot-critical SoC nodes bootph-pre-ram
From: Hung-Chun Tseng
Date: Mon Oct 12 2026 - 19:59:07 EST
A bootloader SPL that follows the K1 BootROM runs from SRAM before DRAM
is up. It needs the root clocks, the clock and reset controllers, the
console UART, and the boot media controllers: SD (sdhci0), eMMC and
QSPI NOR. Mark these nodes bootph-pre-ram so an SPL can use the
upstream device tree as is, instead of carrying the tags in per-board
overlays.
These are the SoC nodes that the mainline U-Boot SPL for K1 currently
tags in its board -u-boot.dtsi files.
Assisted-by: claude-opus-5-5 dtbs_check
Signed-off-by: Hung-Chun Tseng <alan.tseng.cs@xxxxxxxxx>
---
arch/riscv/boot/dts/spacemit/k1.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 3fabfd341..8ca98d15a 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -322,6 +322,7 @@ cluster1_l2_cache: l2-cache1 {
clocks {
vctcxo_1m: clock-1m {
compatible = "fixed-clock";
+ bootph-pre-ram;
clock-frequency = <1000000>;
clock-output-names = "vctcxo_1m";
#clock-cells = <0>;
@@ -329,6 +330,7 @@ vctcxo_1m: clock-1m {
vctcxo_24m: clock-24m {
compatible = "fixed-clock";
+ bootph-pre-ram;
clock-frequency = <24000000>;
clock-output-names = "vctcxo_24m";
#clock-cells = <0>;
@@ -336,6 +338,7 @@ vctcxo_24m: clock-24m {
vctcxo_3m: clock-3m {
compatible = "fixed-clock";
+ bootph-pre-ram;
clock-frequency = <3000000>;
clock-output-names = "vctcxo_3m";
#clock-cells = <0>;
@@ -343,6 +346,7 @@ vctcxo_3m: clock-3m {
osc_32k: clock-32k {
compatible = "fixed-clock";
+ bootph-pre-ram;
clock-frequency = <32768>;
clock-output-names = "osc_32k";
#clock-cells = <0>;
@@ -586,6 +590,7 @@ i2c5: i2c@d4013800 {
syscon_apbc: system-controller@d4015000 {
compatible = "spacemit,k1-syscon-apbc";
reg = <0x0 0xd4015000 0x0 0x1000>;
+ bootph-pre-ram;
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
<&vctcxo_24m>;
clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
@@ -857,6 +862,7 @@ pwm19: pwm@d4022c00 {
syscon_mpmu: system-controller@d4050000 {
compatible = "spacemit,k1-syscon-mpmu";
reg = <0x0 0xd4050000 0x0 0x209c>;
+ bootph-pre-ram;
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
<&vctcxo_24m>;
clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
@@ -869,6 +875,7 @@ syscon_mpmu: system-controller@d4050000 {
pll: clock-controller@d4090000 {
compatible = "spacemit,k1-pll";
reg = <0x0 0xd4090000 0x0 0x1000>;
+ bootph-pre-ram;
clocks = <&vctcxo_24m>;
spacemit,mpmu = <&syscon_mpmu>;
#clock-cells = <1>;
@@ -877,6 +884,7 @@ pll: clock-controller@d4090000 {
syscon_apmu: system-controller@d4282800 {
compatible = "spacemit,k1-syscon-apmu";
reg = <0x0 0xd4282800 0x0 0x400>;
+ bootph-pre-ram;
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
<&vctcxo_24m>;
clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
@@ -956,6 +964,7 @@ uart0: serial@d4017000 {
compatible = "spacemit,k1-uart",
"intel,xscale-uart";
reg = <0x0 0xd4017000 0x0 0x100>;
+ bootph-pre-ram;
clocks = <&syscon_apbc CLK_UART0>,
<&syscon_apbc CLK_UART0_BUS>;
clock-names = "core", "bus";
@@ -1085,6 +1094,7 @@ qspi: spi@d420c000 {
reg = <0x0 0xd420c000 0x0 0x1000>,
<0x0 0xb8000000 0x0 0xc00000>;
reg-names = "QuadSPI", "QuadSPI-memory";
+ bootph-pre-ram;
clocks = <&syscon_apmu CLK_QSPI_BUS>,
<&syscon_apmu CLK_QSPI>;
clock-names = "qspi_en", "qspi";
@@ -1328,6 +1338,7 @@ usb_dwc3: usb@c0a00000 {
sdhci0: mmc@d4280000 {
compatible = "spacemit,k1-sdhci";
reg = <0x0 0xd4280000 0x0 0x200>;
+ bootph-pre-ram;
clocks = <&syscon_apmu CLK_SDH_AXI>,
<&syscon_apmu CLK_SDH0>;
clock-names = "core", "io";
@@ -1341,6 +1352,7 @@ sdhci0: mmc@d4280000 {
emmc: mmc@d4281000 {
compatible = "spacemit,k1-sdhci";
reg = <0x0 0xd4281000 0x0 0x200>;
+ bootph-pre-ram;
clocks = <&syscon_apmu CLK_SDH_AXI>,
<&syscon_apmu CLK_SDH2>;
clock-names = "core", "io";
--
2.43.0